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Method for Uniformly Coating Insulation Layer on Inner Wall of TSV

A technology of through-silicon vias and insulating layers, applied in the field of wafer-level chip size packaging technology, can solve the problems of high price, difficult spraying method, high temperature of inorganic insulation process, etc., and achieve the effect of improving uniformity and saving equipment cost

Active Publication Date: 2017-12-22
HUATIAN TECH KUNSHAN ELECTRONICS
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

At present, the TSV industry generally uses plasma-enhanced chemical vapor deposition (PECVD) equipment to achieve the coating of the inorganic insulating layer, but PECVD equipment is expensive, and the temperature of the inorganic insulation process is relatively high, which is not suitable for the process temperature required by the image sensor. Technical indicators below 200 degrees
However, the existing commonly used spin coating equipment has strict requirements on the viscosity of insulating materials, and the spraying method is difficult to ensure that the entire inner wall of the TSV can be coated evenly to achieve good insulation.

Method used

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  • Method for Uniformly Coating Insulation Layer on Inner Wall of TSV

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Embodiment Construction

[0028] Such as figure 1 As shown, a method for evenly coating the inner wall of a through-silicon via with an insulating layer, the steps are as follows:

[0029] a. Provide a wafer to be coated with micron-scale TSVs with an aspect ratio greater than or equal to 2:1 and a spin coating machine, place the wafer on the working platform of the spin coating machine, and Make the orifice of the TSV on the wafer surface upward; during specific implementation, place the wafer to be coated containing the TSV with the orifice upward on the working platform of the rotary coating machine, and turn on the vacuum adsorption to ensure No slippage during wafer rotation. Among them, the spin coating machine is a commonly used spin coating equipment in the prior art; through-silicon vias refer to through-silicon vias on the order of microns and with an aspect ratio greater than or equal to 2:1, which are used for conduction on the back of the chip metal PIN. .

[0030] b. Add a certain amou...

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Abstract

The invention discloses a method for coating a silicon through hole inner wall with an insulation layer. The surface of a wafer and the interior of a silicon through hole are cleaned through a cleaning process; the surface of the wafer and the interior of the silicon through hole are rotationally coated with an organic solvent capable of dissolving high-performance polymer materials in advance, then the surface of the wafer and the interior of the silicon through hole are rotationally coated with high-temperature polymer materials, and the high-performance polymer materials are evenly diffused under the effect of the organic solvent, so that the silicon through hole side wall is evenly coated with the insulation layer. According to the method, the wafer surface and the wafer silicon through hole side wall and bottom can be evenly coated with the insulation layer on standard rotary coating equipment through the general technology at normal temperature, the micron dimension silicon through hole three-dimensional even coating is achieved, the equipment cost is greatly saved, the uniformity of the silicon through hole insulation layer is improved, and binding force between the insulation layer and materials making contact with the insulation layer is improved.

Description

technical field [0001] The invention relates to the field of wafer level chip scale packaging (WLCSP) technology of semiconductor chips, in particular to a method for uniformly coating the inner wall of a through-silicon hole with an insulating layer. Background technique [0002] Wafer level chip scale packaging (wafer level chip scale packaging, WLCSP) is a kind of IC packaging method. It is a packaging method that first packages the entire wafer and then cuts it to obtain a single chip. Using through-silicon via technology to expose the pins on the front of the metal chip, that is, the PIN pins, from the back of the wafer, and then electrically lead them to the back of the wafer, the size of the chip after packaging can be kept unchanged, and it has an extremely short The electrical transmission distance makes the chip run faster and the power is reduced. [0003] The through-silicon via (TSV) technology needs to insulate the inner wall of the through-silicon via before ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L21/31
CPCH01L21/31H01L21/76831H01L2221/1057
Inventor 范俊黄小花王晔晔沈建树翟玲玲钱静娴
Owner HUATIAN TECH KUNSHAN ELECTRONICS