Data anti-attack method, data anti-attack device, RSA modular exponentiation operation method, RSA modular exponentiation operation device and circuit
A computing method and anti-attack technology, applied in the field of data security, can solve problems such as security risks, improve security, reduce the possibility of key information, and avoid power consumption differences
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Embodiment 1
[0067] refer to image 3 , the embodiment of the present invention provides a data attack defense method, the attack defense method may include the following steps:
[0068] Step 300: Obtain data;
[0069] Step 302: Write the value of the data bit to be judged in the data into the first register, the value of the data bit is the first value or the second value, and set the values of other data bits in the first register to is the first value;
[0070] Wherein, the first register may be an ACC register.
[0071] The size of the data may be 1 byte, or data of other sizes, which can be selected by those skilled in the art according to the capability of the operation circuit applying the RSA algorithm. Taking the data size as 1 byte as an example, the data has 8 data bits in total, and the size of each data bit is 1 bit, then the data bit to be judged may be any one of the data.
[0072] After a certain bit of the data is processed by using the attack defense method describe...
Embodiment 2
[0093] refer to Figure 4 , this embodiment provides a data attack defense device 40, the device 40 may include:
[0094] The first writing unit 402 is used to write the value of the data bit to be judged in the data into the first register 410, the value of the data bit is the first value or the second value, and the value of the first register 410 The values of other data bits are set as the first value;
[0095] A judging unit 404, configured to judge whether the value of the data bit in the first register 410 is an odd number of the second value;
[0096] The second writing unit 406 is used to write the second value into the second register 420 when the value of the data bit is an odd number of the second value, and when the value of the data bit is an odd number of the second value When the number is an even number, write the first value into the second register 420;
[0097] The reading unit 408 is configured to read the value of the second register 420, and use the...
Embodiment 3
[0103] refer to Figure 5 , this embodiment provides an RSA modular exponentiation circuit, and the RSA modular exponentiation circuit may include: a processor 50, a first register 510 connected to the processor 50, a first register 510 connected to the processor 50, Two registers 520, and a multiplier 530 connected to the processor 50.
[0104] In a specific implementation, the processor may include:
[0105] The first writing unit 502 is connected with the first register 510, and is used for writing the value of the data bit to be judged into the first register 510, and setting the values of other data bits of the first register 510 to is the first value, the value of the data bit is the first value or the second value;
[0106] A judging unit 504, connected to the first register 510, for judging whether the value of the data bit in the first register 510 is an odd number of the second value;
[0107] The second writing unit 506 is connected with the judging unit 504 an...
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