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A preparation method of an array substrate and a display panel thereof, and a mask plate

A technology of mask plate and substrate, which is applied in the preparation of array substrate and its display panel, mask plate field, can solve the problem of high production cost of display panel, achieve the effect of reducing product development and production cost, and reducing the number of use

Active Publication Date: 2019-05-24
BOE TECH GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] In order to solve the above problems, the present invention provides an array substrate, a method for preparing the display panel thereof, and a mask plate, which are used to solve the problem of high production cost of the display panel caused by the mask plate in the prior art

Method used

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  • A preparation method of an array substrate and a display panel thereof, and a mask plate
  • A preparation method of an array substrate and a display panel thereof, and a mask plate
  • A preparation method of an array substrate and a display panel thereof, and a mask plate

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Embodiment 1

[0048] figure 1 It is a schematic structural diagram of a mask plate provided by Embodiment 1 of the present invention. Such as figure 1 As shown, the mask 101 includes a substrate, and the substrate includes a non-light-transmitting region 102 , a partially light-transmitting region 103 and a light-transmitting region 104 . The non-transparent area 102 is provided with a layer of non-transparent material, the partially transparent area 103 is provided with a layer of partially transparent material, the transparent area 104 is not provided with a light-shielding material, and the transparent area 104 is provided with within the partially transparent region 103 . During the patterning process, the transparent region 104 and the partially transparent region 103 are used to form grid lines, gates and common electrode lines, and the transparent region 104 is also used to form the first via hole and the second via hole. holes, so that the gate mask and the via hole mask can be s...

Embodiment 2

[0052] figure 2 It is a schematic structural diagram of a mask plate provided by Embodiment 2 of the present invention. Such as figure 2 As shown, the mask 101 includes a substrate, and the substrate includes a non-light-transmitting region 102 , a partially light-transmitting region 103 and a light-transmitting region 104 . The non-transparent area 102 is provided with a layer of non-transparent material, the partially transparent area 103 is provided with a layer of partially transparent material, the transparent area 104 is not provided with a light-shielding material, and the non-transparent area 102 It is arranged in the partially light-transmitting region 103 . During the patterning process, the non-transparent region 102 and the partially transparent region 103 are used to form gate lines, gates and common electrode lines, and the non-transparent region 102 is also used to form the first via hole and the second via hole. Two via holes, so that the gate mask and the...

Embodiment 3

[0056] In this embodiment, the preparation process of the array substrate is described in detail as follows. It should be noted that the array substrate described in this embodiment is in TN mode, but array substrates in other modes, for example, the preparation methods of array substrates in ADS mode and VA mode also belong to the protection scope of the present invention.

[0057] image 3 It is a flowchart of a method for preparing an array substrate provided in Embodiment 3 of the present invention. Such as image 3 Shown, described preparation method comprises:

[0058] Step 3001, forming a gate metal thin film on a substrate.

[0059] Step 3002, using a mask plate to form gate lines and gates through a patterning process.

[0060] In this embodiment, the mask plate is the mask plate provided in the first embodiment above, and the specific content can refer to the description in the first embodiment above, and will not be repeated here.

[0061] Figure 4a ~ Figure ...

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Abstract

The invention provides an array substrate, a preparation method of a display panel, and a mask plate. The mask plate comprises a baseplate, wherein the baseplate comprises a light-proof area, a partial light-transmission area and a light transmission area; the light-proof area is provided with a light-proof material layer, the partial light-transmission area is provided with a partial-light-transmission material layer, the light transmission area is not provided with a light shading material, the light transmission area is arranged in the partial light-transmission area, or the light-proof area is arranged in the partial light-transmission area. By adopting the mask plate, the sharing of a grid mask plate and a through-hole mask plate can be realized, so that the use amount of the mask plate can be reduced, and the development and production cost of products can be reduced.

Description

technical field [0001] The invention relates to the field of display technology, in particular to an array substrate, a method for preparing a display panel thereof, and a mask plate. Background technique [0002] In the TFT-LCD manufacturing industry, the manufacturing process of the array substrate requires 4-7 exposure processes, so 4-7 masks are required, for example, the common twisted nematic (Twisted Nematic, TN) mode array The substrate needs a gate mask (Gate Mask), an active layer mask (Active Mask), a source-drain mask (S / D Mask), a via mask (Via Mask), and a pixel electrode mask There are five mask boards in total (ITO Mask). Each mask plate is worth RMB 1-2 million, so it takes a lot of money to buy a mask plate for only one product, which increases the cost of product development and production. Contents of the invention [0003] In order to solve the above problems, the present invention provides an array substrate, a method for preparing the display panel...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G03F1/54H01L21/77G03F1/60G02F1/13
CPCG02F1/1303G03F1/54G03F1/60H01L21/77H01L2021/775
Inventor 白金超刘耀刘晓伟丁向前郭总杰
Owner BOE TECH GRP CO LTD
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