A signal generator and signal generating method for generating integer frequency pulses
A technology of signal generator and integer frequency, which is applied in the field of signal processing, can solve the problem of non-integer cycle counting of output pulses, and achieve the effect of high precision and easy realization
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0034] The signal connection relation between each module of embodiment 1 is as follows figure 2 As shown, wherein, Clk is a system clock signal, Rst_n is a system reset signal, Div_en is a division enable signal, Div_done is a division completion enable pulse signal, Run is a pulse output enable signal, and pnm is a pulse output port;
[0035] f is the input frequency, and the input frequency value f can be set according to requirements; the division enable signal Div_en output by the detection module is used as the drive enable signal of the division module;
[0036] When the division module receives the division enable signal Div_en, it performs division calculation on the rising edge of the next system clock cycle, the dividend is the frequency value of the system clock signal written into the division module, and the divisor is the input frequency value f;
[0037] After the division module completes the division calculation, it outputs the division completion enable sig...
specific Embodiment 1 and Embodiment 2
[0044] Below in conjunction with specific embodiment 1 and embodiment 2, the working principle of the present invention is specifically set forth as follows:
[0045] When the remainder R is non-zero, it indicates that the counting cycle of the pulse corresponding to the input frequency should be greater than Q, less than a decimal number of (Q+1), set as A; the purpose of the present invention is to convert the decimal number A into R integers (Q+1) and (f-R) integer Q average value, that is, A=[R*(Q+1)+(f-R)Q] / f; output unit time with (Q+1) as the counting period R pulses, (f-R) pulses with Q as the counting period, and the output pulse signals of the two counting periods are evenly distributed;
[0046] When the remainder R is zero, R pulses with (Q+1) as the counting period and (f-R) pulses with Q as the counting period are output per unit time, and the output pulse signals of the two counting periods are evenly distributed;
[0047] If the system clock frequency used is ...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 


