Signal generator and signal generation method for generating integer frequency pulses
A signal generator and integer frequency technology, which is applied in the field of signal processing, can solve the problem of non-integer cycle counting of output pulses, and achieve the effect of high precision and easy realization
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Embodiment 1
[0034] The signal connection relationship between the modules of Example 1 is as follows figure 2 As shown, Clk is the system clock signal, Rst_n is the system reset signal, Div_en is the division enable signal, Div_done is the division completion enable pulse signal, Run is the pulse output enable signal, and pnm is the pulse output port;
[0035] f is the input frequency, and the input frequency value f can be set as required; the division enable signal Div_en output by the detection module is used as the drive enable signal of the division module;
[0036] After the division module receives the division enable signal Div_en, it performs division calculation on the rising edge of the next system clock cycle. The dividend is the frequency value of the system clock signal written in the division module, and the divisor is the input frequency value f;
[0037] When the division module completes the division calculation, it outputs the division completion enable signal Div_done, quotie...
specific Embodiment 1 and Embodiment 2
[0044] The working principle of the present invention is specifically described as follows in combination with specific embodiment 1 and embodiment 2.
[0045] When the remainder R is non-zero, it indicates that the counting period of the pulse corresponding to the input frequency should be a decimal number greater than Q and less than (Q+1), set as A; the purpose of the present invention is to convert the decimal A into R integers (Q+1) and (fR) the average value of integer Q, that is, A=[R*(Q+1)+(fR)Q] / f; output R with (Q+1) as the counting period in unit time Pulses, with Q as the counting period (fR) pulses, the output pulse signals of the two counting periods are evenly distributed;
[0046] When the remainder R is zero, R pulses with (Q+1) as the counting period and (f-R) pulses with Q as the counting period are output per unit time, and the output pulse signals of the two counting periods are evenly distributed;
[0047] If the system clock frequency used is f clk , The cloc...
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