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A kind of preparation method of fs-igbt

A silicon chip and backside technology, applied in the field of power semiconductor devices, can solve the problems of silicon chip warping, difficulty, silicon chip size limitation, etc., and achieve the effect of reduced forward conduction voltage and small turn-off loss

Inactive Publication Date: 2017-05-10
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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Problems solved by technology

[0008] The purpose of the present invention is to propose a method for preparing FS-IGBT on a thick silicon wafer to solve the complex and difficult preparation process caused by thin silicon wafers during the preparation process of medium and low voltage FS-IGBTs, warping of silicon wafers, Deformation, fragmentation, limited size of silicon wafer (wafer), low yield, high cost, difficulty in realizing industrialization, and huge problems caused by thin silicon wafers in subsequent wafer dicing and chip packaging technical challenge

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[0038] The principles and characteristics of the present invention will be further described below in conjunction with the accompanying drawings, and the examples given are only for explaining the present invention, and are not intended to limit the scope of the present invention.

[0039] Such as Image 6 As shown, the present invention provides a kind of method that prepares FS-IGBT with thin drift region on thick silicon chip, comprises:

[0040] Step 1: Select two N-type monocrystalline silicon wafers as the first silicon wafer and the second silicon wafer. The thickness of the first silicon wafer is 300 microns, and lightly doped FZ silicon is used with a doping concentration of 2.5*10 14 piece / cm 3 , to form Figure 5 In the drift region 3 of the FS-IGBT mentioned in the above, the thickness of the second silicon wafer is 300 microns, and heavily doped CZ silicon is used, and the doping concentration is 5*10 19 piece / cm 3 , to form Figure 5 The back N+ region 11 of...

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Abstract

The invention provides a method for preparing FS-IGBT on a thick silicon wafer, which is used to solve the complex and difficult preparation process caused by thin silicon wafers, warping, deformation, and fragmentation of silicon wafers during the preparation process of medium and low voltage FS-IGBTs. , the size of the silicon wafer is limited, the yield rate is low, the cost is high, and it is difficult to achieve industrialization, as well as the huge technical challenges brought about by the thin silicon wafer in the subsequent wafer dicing and chip packaging. Select lightly doped FZ silicon as the first silicon wafer, and heavily doped CZ silicon or FZ silicon as the second silicon wafer. First, make an N-type FS layer and a P-type transparent collector region on the back of the first silicon wafer. Then bond the first and second silicon wafers, then thin the first silicon wafer, make the front structure, and finally thin the second silicon wafer, and then form the collector electrode by etching, depositing metal, and chemical mechanical polishing; that is, the prepared FS‑IGBTs.

Description

technical field [0001] The invention belongs to the technical field of power semiconductor devices, and relates to an insulated gate bipolar transistor (IGBT), in particular to a preparation method of a field stop type insulated gate bipolar transistor (FS-IGBT). Background technique [0002] Insulated gate bipolar transistor (IGBT) is a new type of power electronic device combined with MOS field effect and bipolar transistor. The advantages of large current and low loss have become one of the core electronic components in modern power electronic circuits, and are widely used in various fields of the national economy such as communications, energy, transportation, industry, medicine, household appliances, and aerospace. The invention and application of IGBT have played an extremely important role in improving the performance of power electronic systems. Since the 1990s, through the continuous development of device structure and manufacturing technology, commercial mass-produ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/331H01L29/739
Inventor 张金平陈钱李丹郭绪阳朱章丹李泽宏任敏张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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