49 results about "Cz silicon" patented technology

The invention discloses a control system of a high frequency switching power supply for a Cz silicon single crystal furnace and a control method. The control method includes the steps of combining self-adaptive fuzzy control and sliding mode variable structure control, and aiming at a high-frequency switch heating electric power for the Cz silicon single crystal furnace to design a power controller based on a self-adaptive fuzzy control and sliding mode variable structure control method. The control system of the high frequency switching power supply for the Cz silicon single crystal furnace and the control method play respective advantages of fuzzy control and sliding mode variable structure control, further improve dynamic performance of the system, have good robustness for input voltage or load disturbance, and relieve or avoid vibration which generally happens to a sliding mode.

The present invention is directed to a single crystal Czochralski-type silicon wafer, and a process for the preparation thereof, which has at least a surface layer of high resistivity, the layer having an interstitial oxygen content which renders it incapable of forming thermal donors in an amount sufficient to affect resistivity upon being subjected to a conventional semiconductor device manufacturing process. The present invention further directed to a silicon on insulator structure derived from such a wafer.

The invention discloses a carbon-carbon composite guide cylinder of a CZ silicon crystal growing furnace and a preparation method thereof. The cylinder body of the carbon-carbon composite guide cylinder of the CZ silicon crystal growing furnace consists of a surface coating, a carbon-carbon composite layer and a carbon-carbon composite central layer. The preparation method of the carbon-carbon composite guide cylinder comprises the following steps: (1) designing and manufacturing a mold of the guide cylinder; (2) designing the shape and size of carbon fiber felt and cutting and blanking according to the size; (3) preparing a blank; (4) curing the blank; (5) performing CVD densification; (6) demolding the guide cylinder and polishing the surface of the guide cylinder; (7) performing secondary CDV densification; (8) machining the end parts of the guide cylinder and finishing the rest surface of the guide cylinder; (9) subjecting the finished guide cylinder to surface anti-oxidization, anti-erosion and anti-corrosion coating processing; and (10) subjecting the guide cylinder to drying and high-temperature purification processing. The guide cylinder product of the invention has the advantages of high service reliability, long service life and convenient replacing operation; and the preparation method can improve the rate of finished crystals and reduce the energy consumption of crystal pulling by about 10 percent.

A silicon epitaxial wafer of the invention comprises a silicon single crystal wafer sliced from a CZ silicon ingot doped with carbon in a concentration range of not less than 5×10¹⁵ atoms/cm³ and not more than 5×10¹⁷ atoms/cm³ and an epitaxial layer consisting of a silicon single crystal epitaxially grown on a front surface of the silicon single crystal wafer. A polycrystalline silicon layer having a thickness of not less than 0.5 μm and not more than 1.5 μm is formed on a back surface of the silicon single crystal wafer.

Nitrogen-doped CZ silicon crystal ingots and wafers sliced therefrom are disclosed that provide for post epitaxial thermally treated wafers having oxygen precipitate density and size that are substantially uniformly distributed radially and exhibit the lack of a significant edge effect. Methods for producing such CZ silicon crystal ingots are also provided by controlling the pull rate from molten silicon, the temperature gradient and the nitrogen concentration. Methods for simulating the radial bulk micro defect size distribution, radial bulk micro defect density distribution and oxygen precipitation density distribution of post epitaxial thermally treated wafers sliced from nitrogen-doped CZ silicon crystals are also provided.

The invention provides a method for displaying and detecting void type defects in a Czochralski silicon wafer, and the void type defects are displayed by utilizing polyhedron copper precipitation. The method for displaying the void type defects in the Czochralski silicon wafer comprises the following steps of: immersing a polished silicon wafer into a copper nitrate solution for standing; rinsing the silicon wafer in deionized water, taking out and airing; performing heat treatment on the silicon wafer after copper precipitation and airing; quickly cooling the silicon wafer after heat treatment; and horizontally placing the silicon wafer after cooling in a preferential etching solution for etching. The invention further provides the method for detecting the void type defects in the Czochralski silicon wafer, and the method comprises the following steps of: preparing a silicon wafer sample according to the method; and directly observing the polished surface of the silicon wafer sample by an optical microscope or a scanning electron microscope. The polyhedron copper precipitation observed under the microscope corresponds to the void type defects. According to the method provided by the invention, the void type defects in the Czochralski silicon wafer can be clearly displayed within a shorter period of time, the observation can be conveniently performed by adopting the conventional optical microscope under common environments, and the method is suitable for detecting the void type defects in the Czochralski silicon wafer in industrial production.

The invention relates to a CZ (Czochralski) silicon rod doped with boron and phosphorus, and a method for rapidly analyzing the contents of boron and phosphorus in ingredients. The method provided by the invention comprises the following steps: firstly, calculating the head doping concentration of the CZ silicon rod and the doping concentration in a certain length; deriving the contents of the boron and phosphorus in the ingredients of the CZ silicon rod according to the formulas (4), (5) and (6), and converting into the corresponding resistivity; and simultaneously, calculating the resistivity and equivalent resistivity caused by the content of the boron in any length on the silicon rod according to the formula (4). The invention has the advantage of accurate, convenient and rapid calculation, reduces the testing cost and expense of silicon materials, can be used in the aspects of quality identification of solar energy level CZ single crystals, quality identification of semiconductor CZ single crystals, quality identification of the silicon materials and the like, and has wide application prospects.

The invention relates to a solar-grade Czochralski (CZ) silicon single crystal thermal donor control process. The technical problems to be solved are to control the thermal donor concentration at the head of a CZ silicon single crystal and reduce or avoid silicon wafers needing annealing treatment. The process comprises the following main steps of: 1, charging, dissolving, making residues fall, and doping or pre-doping; 2, volatilizing; 3, seeding, shouldering, turning a shoulder, ensuring equal diameter and closing; and 4, closing, catching, lifting the crystal and cooling. Compared with the process in the conventional industry, the process can reduce the thermal donor concentration by 60 to 75 percent, effectively reduces the silicon wafers needing the annealing treatment, reduces cost and improves quality.

Disclosed is an analysis method of boron and phosphor in Ga-doped CZ silicon rod and ingredients. In the method Ga doping concentrations at the head part of the silicon rod and at a certain length of the silicon rod, and doping concentrations at the head part of the CZ silicon rod and at a certain length of the CZ silicon rod when only boron and phosphor are considered are calculated first; boron and phosphor contents in Ga-doped CZ silicon rod ingredients are deduced by formulas (5) and (6), and converted to corresponding resistivity; and an excel data table is created. The invention is a necessary quality control method for Ga-doped solar grade CZ silicon single crystal. Through the invention, the production of solar energy silicon chip is controllable, and product quality and enterprise competitiveness are enhanced.

A method for heat-treating a silicon wafer is provided in which in-plane uniformity in BMD density along a diameter of a bulk of the wafer grown by the CZ process can be improved. Further, a method for heat-treating a silicon wafer is provided in which in-plane uniformity in BMD size can also be improved and COP of a surface layer of the wafer can be reduced. The method includes a step of a first heat treatment in which the CZ silicon wafer is heated to a temperature from 1325 to 1400° C. in an oxidizing gas atmosphere, held at the temperature, and then cooled at a cooling rate of from 50 to 250° C./second, and a step of a second heat treatment in which the wafer is heated to a temperature from 900 to 1200° C. in a non-oxidizing gas atmosphere, held at the temperature, and then cooled.

The invention discloses a seeding method of a Czochralski silicon single crystal. A seeding temperature is regulated by seeding speed deviation, and the seeding speed deviation is a difference value between an average seeding speed and a set seeding speed in a seeding temperature regulation period. If the seeding speed deviation is positive, positive fine adjustment is performed on the seeding temperature; and if the seeding speed deviation is negative, negative fine adjustment is performed on the seeding temperature. According to differences of the diameter shrinkage process, the seeding temperature regulation and control mode comprises the steps that only one continuous diameter shrinkage process is performed in the whole seeding process, regulation and control are conducted in the wholeprocess, and the fine adjustment amount of the seeding temperature is set according to a power regulation coefficient; or the seeding process is a non-continuous diameter shrinkage process and comprises a first diameter shrinkage process, an equal grain refinement process and a second diameter shrinkage process, a target diameter of diameter shrinkage is achieved through the second diameter shrinkage process, once seeding temperature regulation and control is carried out in the equal grain refinement process, and the fine adjustment amount of the seeding temperature is set according to the power regulation coefficient. The invention also discloses a production method of the czochralski silicon single crystal by adopting the seeding method. The temperature is accurately adjusted through seeding, and the yield of single crystals is increased.

The invention provides an auxiliary machine for czochralski silicon single crystal furnace thermal field disassembling and cleaning. The auxiliary machine comprises a supporting frame, a first driving assembly, supporting stand columns, clamping assemblies and tray assemblies, wherein the plurality of supporting stand columns are fixedly installed on the supporting frame, under driving force of the first driving assembly, the telescopic supporting stand columns do lifting motion in the vertical direction, the clamping assemblies are rotationally fixed to the supporting stand columns, the plurality of tray assemblies are rotationally installed on the supporting stand columns, and the clamping assemblies clamp a device in a single crystal furnace and places the device on the tray assemblies. The auxiliary machine is used for disassembling the single crystal furnace in a high-temperature state, so that time required for cooling is saved, and the problem of scalding the personnel is avoided; and in the process of disassembling the single crystal furnace, the rotatable clamping assemblies and the tray assemblies are small in occupied area, the pollution degree to the surrounding environment is reduced, the cleanliness of a workshop is guaranteed, the disassembling efficiency of the single crystal furnace is improved, and potential safety hazards of the workshop are reduced.

The invention provides a n/n+ silicon epitaxial wafer with a high metal impurity absorption capacity, and the n/n+ silicon epitaxial wafer with the high metal impurity absorption capacity includes that a light-doped n-type silicon is an epitaxial layer, defect density of the stacking fault and dislocation is less than or equal to 0.05 /cm2, nitrogen-doped heavy-doped n-type czochralski silicon is a substrate, and the resistivity of the substrate is less than or equal to 0.005 omega cm; the substrate contains a stable oxygen precipitation nucleation center, and the generated density of oxygen precipitation is more than or equal to 1 * 109 / cm3. The invention further provides a preparation method of the n/n+ silicon epitaxial wafer, and the steps of the preparation method include that the heavy-doped n-type czochralski silicon is carried out a high temperature rapid heat treatment under N2 atmosphere, and the light-doped n-type silicon epitaxial layer grows on the heat-treated heavy-doped n-type czochralski silicon. The n/n + silicon epitaxial wafer is acquired through two steps of heat treatment including a low temperature heat treatment and a high temperature heat treatment. The n/n+ silicon epitaxial wafer with a high metal impurity absorption capacity and the preparation method of the n/n+ silicon epitaxial wafer solve the problem that an oxygen precipitation with a high density is hard to generate in the n/n + silicon epitaxial wafer heavy-doped n-type czochralski silicon substrate, and have a good application prospect.

The invention relates to a method for manufacturing a high-voltage VDMOS by adopting a silicon-silicon bonding process. The method comprises the following steps: preparing a support substrate and a bonding substrate; carrying out silicon-silicon bonding on the support substrate and the bonding substrate, and carrying out high-temperature annealing and curing; carrying out a corrosion treatment onthe edge chamfers of the bonded support substrate and the bonding substrate; thinning the bonding substrate to a required thickness; and polishing the bonding substrate. The embodiment of the invention discloses a method for manufacturing a high-voltage VDMOS by adopting a silicon-silicon bonding process. The silicon-silicon bonding process is used; a silicon-silicon bonding sheet is prepared by bonding conventional CZ silicon substrate materials with different resistivity to replace an existing thick-film epitaxial wafer, a high-quality silicon substrate sheet meeting customer requirements isobtained, the production efficiency is improved, the production cost is reduced, a transition region of the obtained high-voltage VDMOS device is obviously narrowed, and the consistency of product parameters is better.

The present invention is a substrate for an electronic device, including a nitride semiconductor film formed on a joined substrate including a silicon single crystal, where the joined substrate has at least a bond wafer including a silicon single crystal joined on a base wafer including a silicon single crystal, the base wafer includes CZ silicon having a resistivity of 0.1 Ωcm or lower and a crystal orientation of <100>, and the bond wafer has a crystal orientation of <111>. This provides a substrate for an electronic device, having a suppressed warp.

The invention provides a modeling method for a czochralski silicon single crystal pulling speed-crystal diameter identification model. The method specifically comprises the following steps: step 1, sampling for multiple times, recording the pulling speeds and crystal diameters of a czochralski silicon single crystal at different sampling moments k, and forming a plurality of groups of data pairs at different sampling moments k; step 2, determining to obtain a specific discrete time nonlinear system model expression about the pulling speed and the crystal diameter of the czochralski silicon single crystal; step 3, training the DBN network; step 4, taking trained DBN network as a czochralski silicon single crystal pulling speed-crystal diameter identification model. According to the modelingmethod of the Czochralski silicon single crystal pulling speed-crystal diameter identification model, the defects existing in training by adopting a DBN network in the prior art are overcome.