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Paralleled decoding system of FAST protocol and realization method of paralleled decoding system

An implementation method and protocol technology, which is applied in the field of decoding system, can solve the problems of high-frequency securities trading delay impact, etc., and achieve the effect of reducing overhead and improving decoding speed

Inactive Publication Date: 2015-06-10
SHANGHAI JIAO TONG UNIV
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Problems solved by technology

These factors affect the latency of high-frequency securities trading at different levels

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  • Paralleled decoding system of FAST protocol and realization method of paralleled decoding system
  • Paralleled decoding system of FAST protocol and realization method of paralleled decoding system

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[0026] The implementation of the present invention is described below through specific examples and in conjunction with the accompanying drawings, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific examples, and various modifications and changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] figure 1 It is a system architecture diagram of a parallel decoding system of the FAST protocol in the present invention. Such as figure 1 As shown, a parallel decoding system of the FAST protocol of the present invention is implemented based on FPGA in a specific embodiment, and it at least includes: a mask module 10 , a command module 20 and a decoding module 30 .

[0028] The ma...

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Abstract

The invention discloses a paralleled decoding system of a FAST protocol and a realization method of the paralleled decoding system. The system comprises a mask module, a command module and a decoding module, wherein the mask module is used for receiving data input and extracting a plurality of most significant digits from input data as stop bit marks to control the output of the mask module; the mask module is used for carrying out field separation on the input data according to a plurality of stop bits; the command module is used for receiving and storing fields divided from the mask module and a state machine is used for controlling the input fields to be matched with FAST template information; the decoding module utilizes four paralleled decoding units and is responsible for decoding the fields transmitted by the command module; each unit is responsible for decoding each field. According to the paralleled decoding system, the paralleled field separation and decoding are carried out so that the decoding speed of the system can be effectively improved; meanwhile, parameterized template information can be stored and the cost for replacing a template can be reduced.

Description

technical field [0001] The present invention relates to a decoding system of the FAST protocol and an implementation method thereof, in particular to an FPGA-based parallel decoding system of the FAST protocol (financial compression protocol) and an implementation method thereof. Background technique [0002] In recent years, with the rapid development of domestic and foreign capital markets, capital mobility has increased and financial transaction methods have become increasingly diversified. As an emerging trading method, high-frequency trading (High-frequency Trading, HFT) is increasingly being highly concerned by practitioners in the financial securities industry. [0003] High-frequency trading is a major algorithmic trading model applied in finance. To be precise, high-frequency trading uses complex technical tools and computer algorithms to quickly trade securities, such as using proprietary trading strategies to buy or sell at the second or even microsecond level th...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F5/06G06Q40/04
Inventor 付宇卓李函刘婷
Owner SHANGHAI JIAO TONG UNIV
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