Method for integrated circuit patterning

An integrated circuit and patterning technology, applied in the field of integrated circuit patterning, can solve the problems of increasing the complexity of processing and manufacturing ICs

Active Publication Date: 2015-09-16
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Such scaling down also increases the complexity of handling and manufacturing ICs, and similar developments in IC processing and manufacturing are required to achieve these advances

Method used

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  • Method for integrated circuit patterning
  • Method for integrated circuit patterning
  • Method for integrated circuit patterning

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Embodiment Construction

[0028] The following disclosure provides many different embodiments or examples for implementing different features of the presented subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to limit the invention. For example, in the following description, forming a first component over or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which a first component may be formed between the first component and the second component. Additional components such that the first and second components may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various instances. This repetition is for the sake of simplicity and clarity and does not in itself indicate a relationship between the ...

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Abstract

Provided is a method of forming a pattern for an integrated circuit. The method includes forming a first layer over a substrate, wherein the first layer's etch rate is sensitive to a radiation, such as an extreme ultraviolet (EUV) radiation or an electron beam (e-beam). The method further includes forming a resist layer over the first layer and exposing the resist layer to the radiation for patterning. During the exposure, various portions of the first layer change their etch rate in response to an energy dose of the radiation received therein. The method further includes developing the resist layer, etching the first layer, and etching the substrate to form a pattern. The radiation-sensitivity of the first layer serves to reduce critical dimension variance of the pattern.

Description

technical field [0001] The present invention relates to methods for patterning integrated circuits. Background technique [0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (ie, the number of interconnected devices per chip area) has generally increased while geometry size (ie, the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. Such scaling down also increases the complexity of handling and manufacturing ICs, and similar developments in IC processing and manufacturing are required in order to achieve these advances. [0003] For example, photoli...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/027G03F7/00
CPCH01L21/31138G03F7/20H01L21/31144H01L21/268H01L21/027G03F7/40H01L21/0332H01L21/0337H01L21/3081H01L21/3086H01L21/31058H01L21/76816H01L29/66795H01L21/0274
Inventor 卢彦丞张书豪游信胜吴瑞庆陈政宏严涛南
Owner TAIWAN SEMICON MFG CO LTD
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