Method for forming integrated circuit

Abstract

In one embodiment, a first dielectric layer (32) that overlies a fuse (16) and a bonding pad (30) is etched with a first etch process. This first etch process exposes a portion (40) of a second dielectric layer (20) that underlies the first dielectric layer (32) and overlies the fuse (16). In addition, the first etch process also forms a bond pad opening (38) that exposes a portion (42) of an anti-reflective layer (28) that forms a portion of the bonding pad (30). A second etch process is then used to etch the exposed portion (42) of the anti-reflective layer (28) and the exposed portion (40) of the second dielectric layer (20) at substantially the same rate to form a fuse window (45) overlying the fuse (16). The second etch process prevents over etching of the second dielectric layer (20), and thus exposure of the underlying fuse (16).

Description

technical field [0001] The present invention relates generally to integrated circuits, and more particularly to methods of forming fuse windows and bond pad holes in integrated circuits. Background technique [0002] The semiconductor industry has led to ever-increasing lithographic patterning problems with the widespread use of highly reflective interconnect materials such as polysilicon, aluminum, refractory metals, and metal silicides to progressively shrink integrated circuit geometries. Unwanted reflections from underlying interconnect material during photoresist patterning cause distortions in the interconnect photoresist pattern and the resulting interconnect. This problem is compounded when photolithographic patterning tools with UV and deep UV exposure wavelengths are used to generate photoresist patterns. [0003] One process suggested to minimize reflections from underlying reflective interconnect material is to form an anti-reflective coating on the photoresist ...

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Problems solved by technology

However, removal of the TiN anti-reflective coating can have detrimental e...

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