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Bit Failure Detection Method Combined with Entity Coordinates

A technology of entity coordinates and coordinates, which is applied in the field of failure analysis method, can solve the problems of time-consuming and labor-intensive failure analysis

Active Publication Date: 2017-11-03
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, current bit failure analysis is labor and time consuming

Method used

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  • Bit Failure Detection Method Combined with Entity Coordinates
  • Bit Failure Detection Method Combined with Entity Coordinates
  • Bit Failure Detection Method Combined with Entity Coordinates

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Embodiment Construction

[0035] figure 1 It is a step diagram of bit failure detection combined with entity coordinates according to the first embodiment of the present invention.

[0036] Please refer to figure 1 , the method of this embodiment first proceeds to step 100 to obtain a wafer alignment detection (wafermapping) data. The so-called wafer alignment detection is to use the inspection machine to align the wafer map with the actual wafer and obtain images, so it can detect each die in the wafer in real time, and target the die in the die. The various defects are marked with different color codes on the wafer map, such as figure 2 as shown ( figure 2 Displayed in black and white but actually in color). The above-mentioned images are generally obtained by scanning electron microscopy (SEM), so they can be saved and named according to the grain location or defect type. In this embodiment, the wafer alignment detection data includes defect images in each layer structure in a single wafer, a...

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Abstract

The invention discloses a bit failure detection method combined with entity coordinates. The bit failure detection method comprises the steps of: acquiring alignment detection data of a wafer, wherein the alignment detection data contains image of defects of each layer in the wafer and entity coordinates of the defects; and carrying out a bit failure detection step to obtain digital coordinates of a failure bit in the wafer, converting the digital coordinates into an entity position, and overlapping the entity position on the entity coordinates so as to obtain relevance between the failure bit and the defects quickly.

Description

technical field [0001] The present invention relates to a Failure Analysis Methodology, and in particular to a bit failure detection method combined with entity coordinates. Background technique [0002] As the line width of the IC process continues to shrink, the precise control and monitoring of components is also more important. From the perspective of nano-generation semiconductor technology, to increase the yield of components, it is necessary to carry out accurate detection and analysis. [0003] The current method for chip failure analysis (failure analysis, FA) includes a technology called Bitmap failure, which can obtain failure bits and find out their physical location, and can (failure item) to predict which layer of the chip internal structure fails. [0004] However, because the cause of the bit failure is unknown, if you want to get the exact cause of the bit failure, you must grind the entire chip under test from the surface to the layer structure that may c...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66
CPCH01L22/30
Inventor 骆统陈琪旻杨令武杨大弘陈光钊
Owner MACRONIX INT CO LTD