Semiconductor memory device and manufacturing method thereof

Abstract

The present invention provides a semiconductor memory device and a manufacturing method thereof. A semiconductor memory device includes stacked gate structures spaced apart from each other along a first direction horizontal to a substrate. Each of the stacked gate structures includes insulating layers and gate electrodes alternately and repeatedly stacked on a substrate. The vertical channel structure penetrates the stacked gate structure. A source plug is disposed between the stacked gate structures. The source wiring is in contact with the substrate and extends along a second direction crossing the first direction. The substrate in contact with the source wiring includes a plurality of protruding regions formed along the second direction. Each of the protruding regions has a first width, and the protruding regions are spaced apart from each other by a first distance greater than the first width.

Description

[0001] Cross references to related applications [0002] This application claims the priority of Korean Patent Application No. 10-2014-0053601 filed at the Korean Intellectual Property Office on May 2, 2014, the entire disclosure of which is incorporated herein by reference. Technical field [0003] The inventive concept relates to a semiconductor memory device and a manufacturing method thereof. More specifically, the inventive concept relates to a three-dimensional (3D) semiconductor memory device and a manufacturing method thereof. Background technique [0004] Semiconductor devices are becoming more highly integrated to provide high performance and low cost. The integration density of semiconductor memory devices directly affects the cost of semiconductor memory devices, thereby leading to a demand for highly integrated semiconductor devices. The degree of integration of conventional two-dimensional (2D) or planar memory devices is mainly determined by the area occupied by a u...

AI Technical Summary

Problems solved by technology

Therefore, techniques for forming fine patterns can greatly affect the integration density of conventional 2D memory devices

However, the integration density of 2D memory devices is still limited even though it continues to increase because extremely expensive equipment is required to form fine patterns.

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