Local bus structure and data interaction method

Abstract

The invention provides a local bus structure used for reliable data communication among a plurality of field programmable gate arrays (FPGA) of a nuclear power instrument control system. The local bus structure comprises a master FPGA, and two or more than two slave FPGAs. The master FPGA and the slave FPGAs transmit data through full duplex parallel buses and are characterized in that the master FPGA and the slave FPGAs are FPGAs with a black-box IP core embedded. The master FPGA comprises a data processing module with cyclic redundancy check (CRC), a bus data transceiving controller, and an input / output (I / O) module. The slave FPGA comprises a data processing module with CRC, a data receiving dual-port RAM, a data sending dual-port RAM, and an I / O module. Through adoption of the bus structure and method, the problem of reliable data communication among the plurality of FPGAs is solved. Due to the self-defined bus manner and self-compiling by the bus controller, the specific requirement that the black box IP cannot be used in the nuclear power industry is met.

Description

technical field [0001] The invention belongs to the technical field of information processing of an industrial DCS (distributed control) system, and relates to a local bus structure and a data interaction method for reliable data communication among multiple FPGAs of a nuclear power instrument control system. Background technique [0002] Based on the design of the more popular digital instrument control system DCS is based on the microprocessor, in order to better achieve the diversity design different from the above DCS and solve the problems of common cause failures, some DCS in the world have begun to use complete DCS design based on FPGA as processor; [0003] However, in order to achieve the independence of module functions in the board, we usually use different FPGA implementations for the platform part and algorithm part of a DCS main control board, and due to the diversity of configuration algorithms, in order to realize different algorithms Parallel and fast opera...

AI Technical Summary

Problems solved by technology

[0004] Since the platform FPGA and the algorithm FPGA adopt a communication method of one master and multiple slaves, the FPGA integrated with the PCI bus IP (Intellectual Property) core can also realize this function, but the embedded IP core is a black box, and the specific verilog of its functional modules The implementation method is not open to users. However, nuclear power plant applications require detailed and complete V&V (Verification&Validation software verification and confirmation) work on functional modules to ensure the safety and reliability of functional blocks. Since the source code of the IP core cannot be obtained, V&V cannot be performed. Complete work, which is not suitable for special applications of nuclear power I&C systems

[0005] And the traditional PCI bus mode that is applied to the microprocessor has the following problems: the PCI bus controller is difficult to write, the signal definition is complicated, and it is difficult to rewrite the logic code; the port level of the PCI bus is fixed, and not all FPGAs support it. Specific level standards; PCI bus does not achieve communication isolation, prone to fault propagation

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