Mixed type three-dimensional on-chip network

Abstract

The embodiment of the invention discloses a mixed type three-dimensional on-chip network. The mixed type three-dimensional on-chip network comprises a plurality of horizontal sub-layers which are stacked in the perpendicular direction, perpendicular buses and a perpendicular bus controller, wherein the same topological structure is kept for horizontal route units in all the horizontal sub-layers, the perpendicular buses are used for connecting the horizontal route units, located on the same vertical line, in the horizontal sub-layers, the number of the perpendicular buses corresponds to the number of the horizontal route units in the horizontal sub-layers, and the perpendicular bus controller is used for controlling the occupation right of the perpendicular buses. The horizontal sub-layers are stacked in the perpendicular direction to form the three-dimensional on-chip network, interconnection in the perpendicular direction is improved, the global interconnection length in a chip is shortened, the bandwidth in the chip is improved, and delay and power consumption of data transmission are reduced.

Description

technical field [0001] The present invention relates to the technical field of on-chip network, and more specifically, relates to a hybrid three-dimensional on-chip network. Background technique [0002] Network-on-Chip (NoC) interconnection structure has become the development trend of chip architecture design, and it is one of the effective solutions for future on-chip IP core interconnection. The multi-core processor system-on-a-chip based on the NoC architecture can realize the separation of computing and communication. The computing subsystem composed of IP cores can independently complete computing tasks, and the communication subsystem composed of NoC is responsible for high-speed data exchange between IP cores. As the integrated circuit process enters the 14nm process era, the design scale of NoC continues to expand. Since all resource nodes are laid out on the plane, and the layout and wiring are carried out on the two-dimensional plane, the interconnection lines be...

AI Technical Summary

Problems solved by technology

The increase of the connection length directly brings about the increase of the system transmission delay, which limits the increase of the data transmission frequency. At the same time, due to the increase of the global connection length and the number of data forwarding times, the communication power consumption of the system will also increase.

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