Check patentability & draft patents in minutes with Patsnap Eureka AI!

Solid-state imaging device

A solid-state imaging device and pixel technology, which is applied in the direction of electric solid-state devices, radiation control devices, transistors, etc., can solve the problems of low-light imaging quality degradation and conversion gain reduction.

Inactive Publication Date: 2015-11-25
KK TOSHIBA
View PDF1 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In a solid-state imaging device, if the capacitance of the voltage conversion unit that converts the charge generated by the pixel into a voltage is increased in order to increase the number of saturated electrons, the conversion gain decreases and the image quality during low-illuminance imaging decreases.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Solid-state imaging device
  • Solid-state imaging device
  • Solid-state imaging device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 Embodiment approach

[0032] figure 1 It is a block diagram showing a schematic configuration of the solid-state imaging device according to the first embodiment.

[0033] exist figure 1 In the solid-state imaging device, a pixel array unit 1 is provided. In the pixel array unit 1 , pixels PC storing photoelectrically converted charges are arranged in a matrix of m (m is a positive integer) rows×n (n is a positive integer) columns along the row direction RD and column direction CD. Further, in the pixel array unit 1 , horizontal control lines Hlin for controlling readout of the pixels PC are provided in the row direction RD, and vertical signal lines Vlin for transmitting signals read from the pixels PC are provided in the column direction CD. In addition, the pixel PC may constitute a Bayer array composed of two green pixels Gr and Gb, one red pixel R, and one blue pixel B. In addition, the pixel array unit 1 is provided with a divided transistor Trmix for dividing a voltage conversion unit int...

no. 2 Embodiment approach

[0057] Image 6 (a) is a cross-sectional view showing a schematic configuration of a part of pixels of the solid-state imaging device according to the second embodiment, Image 6 (b) indicates the first reading Image 6 (a) A diagram of the potential distribution of the structure, Image 6 (c) indicates that at the time of the second readout Image 6 (a) Diagram of the potential distribution of the structure.

[0058] exist Image 6 In the structure of (a), replace Figure 4 The diffusion layer H3 of (a) is provided in the semiconductor layer B2 with diffusion layers H6 and H7 . The diffusion layer H7 is stacked on the diffusion layer H6. In addition, the diffusion layer H6 may be set to be n-type. Diffusion layer H7 can be set to p + type. The diffusion layers H6 and H7 can be used for the floating diffusion FD1. The floating diffusion FD1 can be set to have a deeper potential than the photodiode PD.

[0059] Here, at the time of the first readout, by laminating th...

no. 3 Embodiment approach

[0062] Figure 7 It is a circuit diagram showing a configuration example of a pixel of the solid-state imaging device according to the third embodiment, Figure 8 (a) means Figure 7 A cross-sectional view of the schematic structure of a part of the pixel, Figure 8 (b) indicates the first reading Figure 8 (a) A diagram of the potential distribution of the structure, Figure 8 (c) indicates that at the time of the second readout Figure 8 (a) Diagram of the potential distribution of the structure. exist Figure 7 , in pixel PC′, relative to figure 2 A transfer transistor TRf is added to the pixel PC of . The transfer transistor TRf is arranged between the read transistor TG and the division transistor TRmix.

[0063] In addition, in Figure 8 In the structure of (a), relative to Figure 5 In the structure of (a), the gate electrode G4 is added to the semiconductor layer B3. In addition, a diffusion layer H3' is provided instead of the diffusion layer H3. In addit...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

According to one embodiment, a solid-state imaging device includes a division transistor that divides a voltage converting unit that converts charges generated by a photo diode into a voltage into a first voltage converting unit at a read transistor side and a second voltage converting unit at an amplifying transistor side.

Description

[0001] This application enjoys the priority of Japanese Patent Application No. 2014-102263 filed on May 16, 2014, the entire contents of which are incorporated herein by reference. technical field [0002] Embodiments of the present invention relate to a solid-state imaging device. Background technique [0003] In a solid-state imaging device, if the capacitance of a voltage conversion unit that converts charge generated by a pixel into a voltage is increased in order to increase the number of saturated electrons, the conversion gain decreases and the image quality during low-illuminance imaging decreases. Contents of the invention [0004] The problem to be solved by the present invention is to provide a solid-state imaging device capable of increasing conversion gain without reducing the number of saturation electrons in pixels. [0005] A solid-state imaging device according to one embodiment includes a pixel that stores photoelectrically converted charges, and the pixe...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H04N5/378H04N5/359
CPCH01L27/14603H01L27/14612H01L27/14614H01L27/14641H04N25/59H04N25/70H04N25/767H04N25/778H04N25/134H04N25/78H01L27/146H04N25/75H04N25/709
Inventor 江川佳孝
Owner KK TOSHIBA
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com