A Fixed Bit Width Multiplier with High Accuracy and Low Energy Consumption

Abstract

The invention relates to the technical field of integrated circuits, in particular to a high-precision, low-energy consumption fixed-bit-width multiplier. The high-precision fixed-bit-width multiplier of the present invention includes a CSD encoding circuit, a high-order partial product generation circuit, a low-order compensation circuit, and a partial product compression circuit. The input terminal of the CSD encoding circuit is connected to external input data, and its output terminal is connected to the high-order part. product generation circuit and low compensation circuit; the high-order partial product generation circuit is connected to external input data, and its output terminal is connected to a partial product compression circuit; the low-order compensation circuit is connected to external input data, and its output terminal is connected to a partial product compression circuit; The output terminal of the partial product compression circuit is connected with external output data. The beneficial effect of the invention is that a fixed bit width CSD multiplier with low power consumption and higher speed is realized, and a practical fixed bit width multiplier design with high precision and low energy consumption is realized. The invention is especially suitable for realizing high-precision multiplication with low energy consumption and fixed bit width.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a fixed bit width multiplier with high precision and low energy consumption. Background technique [0002] The multiplier is a very important basic unit in digital integrated circuits. In digital system design, the performance and power consumption of the multiplier largely affect the entire digital system. [0003] In the multiplier design, the encoding circuit is generally used to encode the multiplier to reduce the number of non-zero bits in the multiplier to reduce the generation of partial products, and then reduce the number of adders used to accumulate partial products to simplify hardware. The purpose of reducing power consumption and increasing the speed of multiplication. Among them, the CSD (Canonical Signed Digit) encoder is a redundant signed number encoding method applied to the multiplication operation. Its advantage is that it can reduce ...

AI Technical Summary

Problems solved by technology

The full-precision calculation and truncation method is to truncate the digits with lower weight on the result of the full-precision calculation, and then use the constant compensation method to achieve higher precision, but its power consumption and speed are not superior to the full-precision design. ; Although the direct truncation method has lower power consumption and faster speed, the calculation result has a larger error than the accurate result, so the application value is low

The traditional fixed-bit-width CSD multiplier has obvious shortcomings in the design of the compensation method, which greatly restricts the application range of the fixed-bit-width CSD multiplier.

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