Method for increasing display refreshing rate of multi-channel deep memory logic analyzer

A logic analyzer and deep storage technology, applied in the direction of digital output to display devices, etc., can solve the problems of data compression rate, data compression and decompression time-consuming, limited bus and interface speed, etc., to reduce time and reduce data transmission The effect of reducing the amount of time

Inactive Publication Date: 2015-12-30
UNIV OF ELECTRONIC SCI & TECH OF CHINA
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The first method is limited by the bus and interface speed ultimately adopted by the platform, while the second met

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  • Method for increasing display refreshing rate of multi-channel deep memory logic analyzer
  • Method for increasing display refreshing rate of multi-channel deep memory logic analyzer
  • Method for increasing display refreshing rate of multi-channel deep memory logic analyzer

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[0022] The specific embodiments of the present invention will be described below in conjunction with the accompanying drawings, so that those skilled in the art can better understand the present invention. It should be particularly reminded that in the following description, when the detailed description of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.

[0023] In this embodiment, the multi-channel deep storage logic analyzer of the present invention is a virtual logic analyzer with a PC (personal computer) as the control platform. The number of channels is 132 (128 data channels, 4 clock channels), and the maximum The timing analysis rate is 4GSa / s, the maximum state clock rate is 1.65GSa / s, and the maximum storage depth is 128Mb / channel.

[0024] The hardware design block diagram of the logic analyzer is as figure 1 Shown. The measured signal passes through the active probe, and generates a digital sign...

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Abstract

The invention discloses a method for increasing the display refreshing rate of a multi-channel deep memory logic analyzer, aiming at the bottleneck of transmission and data acquisition. The data of channels in a display region in a hardware acquisition card memory is read by selecting an interested (needed) bus and a corresponding channel, namely only part of data in the hardware memory is read, so that the data transmission amount is reduced, and the data transmission time is shortened. In addition, according to segmented full marks, data reading is started, so that the data can be read without waiting for the state that the hardware memory has a full mark, and the time needed by data acquisition is shortened.

Description

technical field [0001] The invention belongs to the technical field of data domain testing, and more specifically relates to a method for improving the display refresh rate of a multi-channel deep storage logic analyzer. Background technique [0002] Multi-channel deep-memory logic analyzers have become a dominant trend in logic analyzer design. The higher the number of channels, the more signals that can be measured simultaneously. If an uninterrupted stream of captured data is required, the logic analyzer requires memory large enough to record the entire event. Because storage depth = sampling time × sampling resolution, this means that under the premise of ensuring sampling resolution, a large storage depth directly improves the single sampling time, that is, more uninterrupted waveform data can be observed and analyzed; while ensuring Under the condition of sampling time, the sampling frequency can be increased to observe a more realistic signal. [0003] The hardware...

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Application Information

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IPC IPC(8): G06F3/14
Inventor 韩熙利赵贻玖杨万渝翟新元徐伟亮彭雪娇
Owner UNIV OF ELECTRONIC SCI & TECH OF CHINA
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