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Packaging substrate resistance welding processing method

A processing method and technology for packaging substrates, which are applied in the fields of circuits and electronics, and can solve the problems of restricting the performance of packaging substrates, the development of light, thin and miniaturization, the uneven surface of solder resist ink, and the flatness bottom.

Active Publication Date: 2016-01-06
GUANGZHOU FASTPRINT CIRCUIT TECH +2
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the unevenness of the graphics lines on the packaging substrate in the traditional packaging substrate manufacturing method, the surface of the solder resist ink is uneven and flat, and the flatness error is usually greater than 10 μm, which seriously restricts the performance of the packaging substrate and the development of thinness and miniaturization.

Method used

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  • Packaging substrate resistance welding processing method
  • Packaging substrate resistance welding processing method
  • Packaging substrate resistance welding processing method

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Embodiment Construction

[0023] The present invention will be described in further detail below, but the embodiments of the present invention are not limited thereto.

[0024] In the traditional packaging substrate solder mask printing process, since the surface of the package substrate is covered with graphics and the substances in the solder mask ink volatilize during the curing process of the solder mask ink, the solder mask surface of the package substrate is uneven, and the unevenness is generally several microns. The quality requirement that the flatness error is less than the micron level cannot be realized.

[0025] In the solder resist processing method of the packaging substrate in this embodiment, by adjusting the printing times of the solder resist ink and controlling the parameters of exposure, development and curing, the error of the flatness of the solder resist of the package substrate product is less than micron level. Include steps:

[0026] (A) First printing

[0027] Before the f...

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Abstract

The invention relates to a packaging substrate resistance welding processing method, comprising the steps of: printing for the first time: printing a first layer of resistance welding ink on the surface of a core plate; performing windowing for the first time: windowing the first layer of resistance welding ink to obtain a first window; grinding: grinding the surface of the first layer of resistance welding ink to be flat; printing for the second time: printing a second layer of resistance welding ink on the first layer of resistance welding ink and the first window; and performing windowing for the second time: windowing the second layer of resistance welding ink to obtain a second window, wherein the second window is located in the scope of the first window. According to the invention, through twice resistance welding ink printing and twice windowing, the planeness error of the second layer of resistance welding ink on the external surface of the first layer of resistance welding ink is smaller than a micrometer grade; in addition, the second layer of resistance welding ink in the scope of the first layer of resistance welding ink is windowed for the second time to obtain a second window; twice printing does not influence windowing on a packaging substrate.

Description

technical field [0001] The invention belongs to the field of electronics and circuits, and in particular relates to a welding resistance processing method for a packaging substrate. Background technique [0002] In the process of manufacturing the packaging substrate, it is usually necessary to print a layer of solder resist ink on the outer surface of the packaging substrate, and the surface flatness of the solder resist ink not only affects the performance and quality of the packaging substrate, but also affects the thickness of the product. However, in the traditional packaging substrate manufacturing method, due to the unevenness of the graphic lines on the packaging substrate, the surface of the solder resist ink is uneven and the flatness is low. Usually, the flatness error is usually greater than 10 μm, which seriously restricts the performance of the packaging substrate and the development of thinness and miniaturization. Contents of the invention [0003] Based on...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H05K3/28H05K3/00
CPCH05K3/0091H05K3/28H05K3/00H05K3/064H05K3/1216H05K2203/025
Inventor 崔永涛冯汝国李志东
Owner GUANGZHOU FASTPRINT CIRCUIT TECH
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