Thin-type chip packaging structure and manufacturing method thereof
A technology of packaging structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc., and can solve problems such as chip cracking and chip damage
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[0023] First please refer to figure 1 , which is a side view of the package structure according to the first embodiment of the present invention. The present invention provides a packaging structure for thinned chips. In the first embodiment, the packaging structure 1 includes: a substrate 110 , a thinned chip 120 , a reinforcement layer 130 and a sealant 140 .
[0024] The thinned chip 120 refers to a chip with a smaller thickness, for example, the thickness may be less than 80 microns, and preferably less than 35 microns. The thinned chip 120 can be disposed on the substrate 110 and electrically connected to the substrate 110 . The electrical connection method can be an inverse crystal method or a wire bonding method to electrically connect to the substrate 110 , but not limited thereto. In the following, the electrical connection between the thinned chip 120 and the substrate 110 by the wire 121 is used as an example for illustration.
[0025] The strengthening layer 130 ...
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