Best polarity search method for power consumption of three-value FPRM circuit

A search method and power consumption technology, applied in the direction of error correction/detection using linear codes, data representation error detection/correction, error correction/detection using block codes, etc. conducting research, etc.

Active Publication Date: 2016-02-03
NINGBO UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, experts and scholars at home and abroad mainly focus on the polarity conversion technology of multi-valued RM logic circuits, and have not studied the power consumption optimization technology of multi-valued RM circuits.

Method used

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  • Best polarity search method for power consumption of three-value FPRM circuit
  • Best polarity search method for power consumption of three-value FPRM circuit
  • Best polarity search method for power consumption of three-value FPRM circuit

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Experimental program
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Effect test

Embodiment 1

[0059] Embodiment one: a kind of ternary FPRM circuit power consumption optimal polarity searching method comprises the following steps:

[0060] ①Establish the power consumption estimation model of the ternary FPRM circuit:

[0061] ①-1 The three-valued FPRM circuit is expressed as the following form using the three-valued FPRM logic function:

[0062] f p ( x n - 1 , x n - 2 , ... , x 0 ) = ⊕ Σ i = 0 3 n - 1 a i...

Embodiment 2

[0094] Embodiment two: a kind of ternary FPRM circuit power consumption optimum polarity search method, comprises the following steps:

[0095] ①Establish the power consumption estimation model of the ternary FPRM circuit:

[0096] ①-1 The three-valued FPRM circuit is expressed as the following form using the three-valued FPRM logic function:

[0097] f p ( x n - 1 , x n - 2 , ... , x 0 ) = ⊕ Σ i = 0 3 n - 1 a i ...

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Abstract

The invention discloses a best polarity search method for power consumption of a three-value FPRM circuit. The best polarity search method comprises the following steps: at first, expressing a three-value FPRM circuit by use of the three-value FPRM logic function under p polarity, decomposing multi-input operation contained in the three-value FPRM logic function to obtain multiple two-input module 3 addition doors and multiple two-input module 3 multiplication doors under the p polarity, using power consumption generated by the two-input module 3 addition doors and the two-input module 3 multiplication doors as the power consumption of the three-value FPRM circuit under the p polarity, establishing a power consumption estimation model of the three-value FPRM circuit, and finally, using a genetic simulated annealing algorithm to carry out best polarity search on the power consumption of the three-value FPRM circuit to optimize the power consumption of the three-value FPRM circuit. The best polarity search method has the advantages of achieving the best polarity search of the power consumption of the three-value FPRM circuit to optimize the power consumption of the three-value FPRM circuit; 13 MCNC Benchmark circuits are randomly adopted to carry out simulation verification, compared with 0 polarity, in the best polarity of the power consumption searched by the best polarity search method disclosed by the invention, the number of the module 3 addition doors is saved for 57.6% on average, the number of the two-input module 3 multiplication doors is saved for 46.25% on average, and the power consumption is saved for 73.98%.

Description

technical field [0001] The invention relates to a method for optimizing the power consumption of a ternary FPRM circuit, in particular to a method for searching the best polarity of the power consumption of a ternary FPRM circuit. Background technique [0002] With the continuous development of the scale and integration of integrated circuits, digital circuits will inevitably encounter problems such as power consumption, area and speed. Traditional digital circuits mostly use binary logic, but the low information content of binary signals has become the main factor restricting the development of integrated circuits. The multi-valued logic circuit increases the ability to carry information in a single line, which can effectively improve the utilization rate of space or time, reduce the connection of digital systems, and save circuit area and cost. The three-valued logic whose base is 3 has the smallest base in the algebraic system of multi-valued logic, which is easy to impl...

Claims

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Application Information

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IPC IPC(8): H03M13/13
Inventor 厉康平汪鹏君张会红
Owner NINGBO UNIV
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