Device for implementing parallel DDS with wide coverage

Abstract

The invention belongs to the technical field of frequency synthesis and relates to a device for implementing a parallel DDS with wide coverage. The device utilizes parallel internal structure and comprises two phase accumulators, two sine look-up table ROMs, a selector, a DAC, and a LPF module. A frequency control word is simultaneously input into the phase accumulator A and the phase accumulator B. The outputs of the two phase accumulators are output to the sine look-up table ROMs to look up tables separately. Binary amplitude sequences output by the two sine look-up table ROMs are output to the one-out-of-two data selector and then are output in an interlaced way under the control of a clock. The operating reference clock frequency of the phase accumulators, the sine look-up table ROMs, and the selector is fc. Two signals are combined by the selector and then are output to the DAC. The reference clock frequency of the DAC is 2fc. The parallel DDS may effectively expand the output bandwidth of the DDS.

Description

technical field [0001] The invention belongs to the technical field of frequency synthesis, in particular to a wide-coverage parallel DDS implementation device. Background technique [0002] Compared with other frequency synthesis methods, the output bandwidth of DDS is narrower. In theory, the upper limit of the output frequency of DDS is 50% of the clock frequency, but the higher the frequency, the more spurious. In practical applications, the general output frequency is 40% of the clock frequency. , and the digital structure of DDS makes its clock frequency not too high, therefore, the relative bandwidth of DDS is very limited. [0003] When DDS needs to output a wider frequency bandwidth, if the commonly used DDS+PLL scheme is used to multiply the frequency of the DDS output with a phase-locked loop, the output frequency can be increased, but the frequency resolution of the entire frequency synthesis system will be reduced. And it takes a certain locking time for the ph...

AI Technical Summary

Problems solved by technology

[0002] Compared with other frequency synthesis methods, the output bandwidth of DDS is narrower. In theory, the upper limit of the output frequency of DDS is 50% of the clock frequency, but the higher the frequency, the more spurious. In practical applications, the general output frequency is 40% of the clock frequency. , and the digital structure of DDS makes its clock frequency not too high, therefore, the relative bandwidth of DDS is very limited

[0003] When DDS needs to output a wider frequency bandwidth, if the commonly used DDS+PLL scheme is used to multiply the frequency of the DDS output with a phase-locked loop, the output frequency can be increased, but the frequency resolution of the entire frequency synthesis system will be reduced. And the phase-locked loop needs a certain locking time to output stable frequency, so that the system loses the characteristic of frequency-agile

Images