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Rate de-matching and de-interleaving method and device

A technology to solve rate matching and rate matching, applied in digital transmission system, electrical components, error prevention, etc., can solve the problem of high memory chip cost, achieve cost saving, reduce requirements, and reduce storage pressure.

Active Publication Date: 2016-06-15
SANECHIPS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] On the other hand, since the interleaving is processed according to the rhythm of the radio frame, that is, one radio frame starts de-interleaving and de-rate matching, and the decoding is processed according to the rhythm of the transmission time interval (TTI, TransmissionTimeInterval), that is, one TTI will start Once; since the length of a TTI is usually greater than the length of a radio frame, that is to say, the decoder starts to process only after a radio frame of TTI length has been assembled, so when processing according to such a processing rhythm, the decoder’s The required input data must first be buffered in the interleaving memory, so for all TrCHs to be processed, one TTI of data must be stored in the interleaving memory, which makes the memory used for storing data in the first interleaving process very powerful. large storage space;
[0005] It can be seen that in the process of de-interleaving and de-rate matching, the interleaving memory needs to have a very large storage space, that is to say, there is a high requirement for the depth of the interleaving memory, which also makes the cost of the memory chip very high

Method used

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  • Rate de-matching and de-interleaving method and device
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  • Rate de-matching and de-interleaving method and device

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Embodiment 1

[0042] Embodiment 1 of the present invention provides a method for de-rate matching and de-interleaving, such as figure 2 As shown, the method includes the following steps:

[0043] Step 101: During the first deinterleaving process, delete the data that has been repeated or punctured, and write the data without operation into the interleaving memory to generate the first data sequence;

[0044] Specifically, the interleaving memory may be implemented by RAM or the like.

[0045] Specifically, the data refers to the data after the rate matching is performed, and the data after the rate matching is performed includes data that is repeated or punctured, and also includes data that has not performed any operation, that is, no operation;

[0046] Before deleting the duplicated or punched data, you can determine whether the data is duplicated or punched data in the following way:

[0047]Judging whether the rate matching flag in the rate matching pattern corresponding to the data...

Embodiment 2

[0059] Embodiment 2 of the present invention provides a device for de-rate matching and de-interleaving, such as Figure 4 As shown, the de-rate matching and de-interleaving device includes: a first write data unit 41, a read data unit 42 and a second write data unit 43, a data sending unit 44, a decoding unit 45 and a storage unit 46; wherein,

[0060] The first write data unit 41 is used to delete the data that has been repeated or punched, and write the data without operation into the storage unit 46 to generate the first data sequence;

[0061] The read data unit 42 is configured to read the first data sequence in the storage unit 46 according to the rate matching pattern after generating the first data sequence of a specific number of transmission time intervals TTI;

[0062] The second data writing unit 43 is configured to insert 0 into the current position of the read first data sequence to obtain the second data sequence when the rate matching flag is punctured;

[00...

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Abstract

The invention discloses a rate de-matching and de-interleaving method. In a first time de-interleaving process, repeated or slotted data are deleted; the data free from any operation are written in an interleaving memory, thus generating a first data sequence; when the first data sequence with a specific number of TTI (Transmission Time Interval) is generated, the first data sequence in the interleaving memory is read according to a rate matching pattern; when the rate matching mark is slotting, 0 is inserted at the current location of the read first data sequence, thus obtaining a second data sequence; and the second data sequence is sent to a decoder for decoding. The invention also discloses a rate de-matching and de-interleaving device.

Description

technical field [0001] The invention relates to the field of mobile communication, in particular to a method and device for de-rate matching and de-interleaving. Background technique [0002] Interleaving coding can effectively overcome deep fading. Interleaving is divided into two steps, the first interleaving and the second interleaving. Unless otherwise specified, the interleaving mentioned is the first interleaving. The first interleaving is a simple inter-column transformation Block interleaving; rate matching means that the bits on the transport channel are retransmitted or punctured to ensure that the total bit rate of the transport channel (TrCH, TransportCHannel) after multiplexing is the same as the total channel bit rate of the allocated physical channel. [0003] In current de-interleaving and de-rate matching devices, interleaving memory is usually used, for example, random access memory (RAM, RamdomAccessMemory) to cache the interleaved data. Holes or no-op da...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L1/00
CPCH04L1/00
Inventor 张勃王文兵
Owner SANECHIPS TECH CO LTD