Rate de-matching and de-interleaving method and device
A technology to solve rate matching and rate matching, applied in digital transmission system, electrical components, error prevention, etc., can solve the problem of high memory chip cost, achieve cost saving, reduce requirements, and reduce storage pressure.
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0042] Embodiment 1 of the present invention provides a method for de-rate matching and de-interleaving, such as figure 2 As shown, the method includes the following steps:
[0043] Step 101: During the first deinterleaving process, delete the data that has been repeated or punctured, and write the data without operation into the interleaving memory to generate the first data sequence;
[0044] Specifically, the interleaving memory may be implemented by RAM or the like.
[0045] Specifically, the data refers to the data after the rate matching is performed, and the data after the rate matching is performed includes data that is repeated or punctured, and also includes data that has not performed any operation, that is, no operation;
[0046] Before deleting the duplicated or punched data, you can determine whether the data is duplicated or punched data in the following way:
[0047]Judging whether the rate matching flag in the rate matching pattern corresponding to the data...
Embodiment 2
[0059] Embodiment 2 of the present invention provides a device for de-rate matching and de-interleaving, such as Figure 4 As shown, the de-rate matching and de-interleaving device includes: a first write data unit 41, a read data unit 42 and a second write data unit 43, a data sending unit 44, a decoding unit 45 and a storage unit 46; wherein,
[0060] The first write data unit 41 is used to delete the data that has been repeated or punched, and write the data without operation into the storage unit 46 to generate the first data sequence;
[0061] The read data unit 42 is configured to read the first data sequence in the storage unit 46 according to the rate matching pattern after generating the first data sequence of a specific number of transmission time intervals TTI;
[0062] The second data writing unit 43 is configured to insert 0 into the current position of the read first data sequence to obtain the second data sequence when the rate matching flag is punctured;
[00...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 