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Efficient hardware dispatching of concurrent functions in multicore processors, and related processor systems, methods, and computer-readable media

A processor and multi-core technology, applied in computing, concurrent instruction execution, machine execution devices, etc.

Inactive Publication Date: 2016-06-15
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Because functions can be relatively small units of computation, the management overhead incurred by contention management can quickly outweigh the realized benefits of parallel execution of functions

Method used

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  • Efficient hardware dispatching of concurrent functions in multicore processors, and related processor systems, methods, and computer-readable media
  • Efficient hardware dispatching of concurrent functions in multicore processors, and related processor systems, methods, and computer-readable media
  • Efficient hardware dispatching of concurrent functions in multicore processors, and related processor systems, methods, and computer-readable media

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Embodiment Construction

[0021] Referring now to the figures, several exemplary embodiments of the invention will be described. The word "exemplary" is used herein to mean "serving as an example, instance, or instance." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0022] Embodiments of the present invention provide efficient hardware dispatch of parallel functions in multi-core processors and related processor systems, methods, and computer-readable media. In one embodiment, a multi-core processor that provides efficient hardware dispatch of parallel functions is provided. A multi-core processor contains multiple processing cores including multiple hardware threads. The multi-core processor further includes a hardware first-in-first-out (FIFO) queue communicatively coupled to the plurality of processing cores. Multi-core processors also include instruction processing circuitry. The instruction processing ci...

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Abstract

Embodiments of the disclosure provide efficient hardware dispatching of concurrent functions in multicore processors, and related processor systems, methods, and computer-readable media. In one embodiment, a first instruction indicating an operation requesting a concurrent transfer of program control is detected in a first hardware thread of a multicore processor. A request for the concurrent transfer of program control is enqueued in a hardware first-in-first-out (FIFO) queue. A second instruction indicating an operation dispatching the request for the concurrent transfer of program control in the hardware FIFO queue is detected in a second hardware thread of the multicore processor. The request for the concurrent transfer of program control is dequeued from the hardware FIFO queue, and the concurrent transfer of program control is executed in the second hardware thread. In this manner, functions may be efficiently and concurrently dispatched in context of multiple hardware threads, while minimizing contention management overhead.

Description

[0001] priority claim [0002] This application claims priority to U.S. Provisional Patent Application No. 61 / 898,745, filed November 1, 2013, and entitled "EFFICIENT HARDWARE DISPATCHINGOF CONCURRENT FUNCTION SININSTRUCTION PROCESSING CIRCUITS, ANDRELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA," which is incorporated by reference methods are incorporated in this article. [0003] This application also claims priority to U.S. Patent Application No. 14 / 224,619, filed March 25, 2014, and entitled "EFFICIENT HARDWARE DISPATCHING OF CONCURRENT FUNCTIONS IN MULTICORE PROCESSORS, ANDRELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA," which is incorporated by reference All methods are incorporated herein. technical field [0004] The techniques of the present invention relate to the processing of parallel functions in multi-core processor-based systems that provide multiple processor cores and / or multiple hardware threads. Background technique [0...

Claims

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Application Information

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IPC IPC(8): G06F9/30G06F9/38
CPCG06F9/3009G06F9/3851G06F9/30043
Inventor 迈克尔·威廉·帕登埃里克·阿斯穆森·德卡斯特罗·洛波马修·克里斯琴·达根樽井健人克雷格·马修·布朗
Owner QUALCOMM INC
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