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Address transition unit supporting deformation radix 16FFT algorithm parallel access

An address conversion and memory address technology, which is applied in the field of address conversion units that support parallel memory access by the deformed radix 16FFT algorithm, can solve the problems of multiple clock cycles, occupation, and inability to output in parallel and sequentially, and achieves low hardware overhead and improved operation. efficacy effect

Active Publication Date: 2016-06-22
NAT UNIV OF DEFENSE TECH
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Problems solved by technology

However, due to the bitreversal operation required at the beginning or end of the FFT operation, this brings difficulties to parallel input or output
For example, when implementing the frequency-domain FFT algorithm, the input of data is sequential and parallel input, but when the result is output, a bit reverse operation is required, which brings challenges to the sequential parallel output of the operation results
If no measures are taken, the output of operation results will take up more clock cycles because they cannot be output in parallel and in sequence

Method used

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  • Address transition unit supporting deformation radix 16FFT algorithm parallel access
  • Address transition unit supporting deformation radix 16FFT algorithm parallel access
  • Address transition unit supporting deformation radix 16FFT algorithm parallel access

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Embodiment Construction

[0026] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0027] The present invention is aimed at a 512-point high-performance dedicated FFT processor, and proposes an address conversion unit that supports four-way deformation base 16 parallel memory access. It can support conflict-free continuous data flow access for FFT operations at extremely low hardware costs. memory, which fully develops the computing power of the butterfly computing unit.

[0028] like figure 1 and Figure 4 As shown, the address conversion unit of the present invention that supports the parallel memory access of the deformed base 16FFT algorithm includes 16 identical address conversion circuits, and each address conversion circuit is composed of a three-input XOR gate and three two-input XOR gates, It is used to realize the conversion of the memory access or result output of the operation to the memory access addr...

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Abstract

The invention discloses an address transition unit supporting deformation radix 16FFT algorithm parallel access; the address transition unit comprises 16 same address transition circuits; each address transition circuit comprises a three-input XOR gate or three two-input XOR gates, so the circuit operation access or result output can realize transition of the access address formed by original memory bank low bit address addressing. The novel method is simple in realization, and small in hardware cost.

Description

technical field [0001] The invention mainly relates to the field of FFT processors, in particular to an address conversion unit which is suitable for high-throughput special-purpose FFT processors and supports parallel memory access of a deformed base 16FFT algorithm. Background technique [0002] At present, in order to promote the development of the wireless communication field, IEEE has established various standards, such as IEEE802.11a / g / n, 802.15.3c, IEEE802.16e and IEEE802.16e and other standards. With the development of applications, the field of wireless communication puts forward higher and higher requirements on the real-time and processing speed of FFT processors. For example, the 802.15.3c standard designed for high-speed wireless personal area networks (WPANs, high-rateWirelessPersonalAreaNetworks) requires that the FFT calculation time of 512 points is not greater than 222.2 nanoseconds. The processing clock of the processor is one-eighth of the sampling frequ...

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Application Information

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IPC IPC(8): G06F12/10G06F17/14
CPCG06F12/10G06F17/14
Inventor 陈海燕杨超刘胜刘宗林刘仲万江华陈胜刚马胜陈俊杰雷元武
Owner NAT UNIV OF DEFENSE TECH
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