Power-on reset circuit applied to high-speed protocol processor chip

Abstract

The invention discloses a power-on reset circuit applied to a high-speed protocol processor chip. The power-on reset circuit comprises a power source end and a reset control circuit. The reset control circuit comprises a voltage detecting module and a reset control module. The voltage detecting module is used for monitoring the power source voltage of the power source end in real time. The reset control module is used for starting reset action when the power source voltage is smaller than or equal to a first voltage threshold value, and stopping the reset action when the power source voltage is larger than or equal to a second voltage threshold value. It is clear that the power source voltage of the power source end is detected and compared with the first voltage threshold value and the second voltage threshold value, reset starting or reset stop are controlled through the comparison result, and due to the fact that the power-on reset circuit does not depend on an external capacitor, a very good reset effect and secondary reset effect are achieved in the fast power-off and power-on process, and reset reliability is improved.

Description

technical field [0001] The invention relates to the technical field of chip design, in particular to a power-on reset circuit applied to a high-speed protocol processor chip. Background technique [0002] At present, in the design of high-speed protocol processor system, in view of the fact that when multiple different types of protocol messages enter the protocol processor for protocol processing, a huge protocol processing state machine is required for protocol analysis and conversion processing, corresponding to various complex scenarios, It needs to occupy extremely large design resources, and the requirements for reset conditions are extremely strict in the design verification process, which not only needs to be accurate but also needs to occupy relatively small resources. For a huge circuit design, reset is a huge challenge, and the effect of reset directly determines the reliability and performance of the chip. [0003] In the prior art, the commonly used technical m...

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Problems solved by technology

However, this circuit has the following disadvantages: the capacitor is too small, so that the reset is completed at a lower power supply voltage, and the system cannot be reset normally. Even if the delay time can be increased by increasing the capacitor value, the capacitor value is too large to be integrated, and Due to the residual charge in the capacitor, it is easy to cause the secondary reset to fail during rapid power-off and power-on.

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