NVM erasing and writing control method and system based on heterogeneous hybrid memory

A hybrid memory and write control technology, applied in the computer field, can solve the problems of limited total number of erasing and writing of NVM, inapplicable NVM memory, limited service life of NVM, etc.

Active Publication Date: 2016-07-20
EVOC SMART IOT TECH CO LTD
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Problems solved by technology

[0004] NVM in heterogeneous hybrid memory is different from DRAM in characteristics. NVM has a congenital defect that the total number of erasing and writing is limited. After reaching a certain number of erasing and writing, NVM will fail, so the service life of NVM is limited. The service life is determined by the maximum erasable The number of writes is determined by t...

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  • NVM erasing and writing control method and system based on heterogeneous hybrid memory
  • NVM erasing and writing control method and system based on heterogeneous hybrid memory
  • NVM erasing and writing control method and system based on heterogeneous hybrid memory

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[0060] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0061] In one embodiment, such as figure 1 As shown, a kind of NVM memory erasure control method based on heterogeneous mixed memory is provided, and this method comprises:

[0062] In step S110, the NVM page erasing times recording table is obtained, and the NVM page erasing times recording table records the page number of the NVM memory and the corresponding erasing times.

[0063] In this embodiment, the NVM memory is paged according to the preset physical page unit, and a page number is assigned to each page after paging. If the page corresponding to the page number has data written, the numbe...

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Abstract

The invention provides a NVM erasing and writing control method based on a heterogeneous hybrid memory. The method comprises the following steps of: obtaining a NVM page erasing and writing time recording table, wherein the page serial number of a NVM and the corresponding erasing and writing time are recorded in the NVM page erasing and writing time recording table; according to the NVM page erasing and writing time recording table, operating the erasing and writing time corresponding to the page serial number of the NVM by adopting a balancing algorithm so as to obtain the operation value of the erasing and writing time; and writing data in the NVM according to the page of the NVM, the page serial number of which is the operation value. Because the balancing algorithm can ensure that the selection times of all pages of the NVM are relatively random and average, the erasing and writing times of different storage units of the NVM are controlled; the service lives of various storage units are relatively average; and the invention further provides a NVM erasing and writing control system based on the heterogeneous hybrid memory.

Description

technical field [0001] The invention relates to the technical field of computers, in particular to a method and system for controlling erasing and writing of NVM memory based on heterogeneous hybrid memory. Background technique [0002] With the development of emerging non-volatile random storage medium (Non-VolatileMemory, NVM) technology represented by resistance memory, ferroelectric memory, phase change memory, etc., the development of storage technology has been promoted, and new memory and storage architectures have been developed. A good foundation has been laid. By combining the new NVM and Dynamic Random Access Memory (Dynamic Random Access Memory, DRAM), a hybrid memory architecture is built to form a heterogeneous hybrid memory. Heterogeneous hybrid memory has the characteristics of NVM and DRAM at the same time. It not only has the function of conventional memory, but the data stored in DRAM will disappear immediately after power off, which is volatile; at the s...

Claims

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Application Information

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IPC IPC(8): G06F12/08G06F3/06G06F17/30
Inventor 薛英仪马先明庞观士陈志列王志远沈航梁艳妮徐成泽
Owner EVOC SMART IOT TECH CO LTD
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