A Parallel Testing Method of IC Card Based on Single IO

Abstract

The invention provides an IC card parallel test method based on single IO, and relates to the technical field of IC cards. A tester is used to carry out parallel test on a chip of the IC card to be tested. The parallel test method comprises a command reception method of the card and a data sending method of the card, an internal clock sampling command IO is used, and receiving and transmitting commands are aligned each bit. The command reception method of the card comprises the steps that 1) low level of an external clock period serves as an initial mark; 2) the IC card to be tested uses the internal clock sampling command IO to sample and count the length of high and low levels; 3) the IC card to the tested counts each group of high and low levels and carry out determination; and 4) the type of command bit 0-bit 2 is transmitted, namely, the length of the command is determined, the IC card to be tested carries out sampling sequentially, the cycle of command reception is skipped out after that specific length of data is received. According to the invention, the internal clock sampling command IO is used, the commands are aligned every bit, the clock IO is reduced, the amount of cards tested simultaneously is increased, and the test cost is reduced effectively.

Description

technical field [0001] The invention relates to the technical field of IC cards, in particular, parallel testing can be performed on a plurality of IC cards without an external clock. Background technique [0002] IC cards are widely used in applications such as mobile phone communication and credit card payment. With the continuous advancement of IC card technology, the unit area of ​​IC cards is shrinking day by day, and the output value on a single wafer continues to increase. Accompanying it is that the proportion of test cost to the total cost increases significantly, and this contradiction becomes more and more obvious as the storage capacity of the IC card becomes larger. [0003] In the prior art, because the internal clock of the chip on the IC card, that is, the clock generated by the internal crystal oscillator, has a certain range of deviation, so the traditional production test uses an external clock, that is, the clock sent by the testing machine for parallel ...

AI Technical Summary

Problems solved by technology

The cost is that each chip needs two IOs provided by the testing machine, that is, command IO and clock IO, which cannot maximize the number of cards tested at the same time.

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