FPGA (Field Programmable Gate Array) binary file compression and decompression method, and FPGA binary file compression and decompression device

A binary file and compression method technology, applied in the field of FPGA, can solve problems that are not conducive to improving the overall compression ratio and overall compression performance

Active Publication Date: 2016-12-07
深圳市恒扬数据股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The purpose of the embodiments of the present invention is to provide a method for compressing FPGA binary files, which aims to solve the problem that current general compression al

Method used

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  • FPGA (Field Programmable Gate Array) binary file compression and decompression method, and FPGA binary file compression and decompression device
  • FPGA (Field Programmable Gate Array) binary file compression and decompression method, and FPGA binary file compression and decompression device
  • FPGA (Field Programmable Gate Array) binary file compression and decompression method, and FPGA binary file compression and decompression device

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Embodiment 1

[0037] figure 1 It is the realization flowchart of the FPGA binary file compression method that the embodiment of the present invention provides, is described in detail as follows:

[0038] In step S101, obtain the FPGA binary file;

[0039] In step S102, traverse the content of the FPGA binary file, classify the content, determine the data area where the classified data and the classified data are located;

[0040] Wherein, the data area includes: a fixed data area, a repeated data area, a sparse data area and a random data area;

[0041] The fixed data area is: the data area shared by each FPGA binary file;

[0042] The repeated data area is: a data area that stores all 0s or all 1s;

[0043] The sparse data area is: a data area storing four-byte data;

[0044] The random data area is: a data area for storing random data.

[0045] In step S103, the coded storage method corresponding to the data area is used to encode and store the classified data;

[0046] In step S104...

Embodiment 2

[0064] figure 2 It is the realization flowchart of the FPGA binary file compression method step S102 that the embodiment of the present invention provides, and is described in detail as follows:

[0065] In step S201, traverse the content of the FPGA binary file;

[0066] In step S202, according to the traversed content and the pre-configured data area determination function, the content is classified, and the classified data and the data area where the classified data is located are determined.

Embodiment 3

[0068] The implementation flowchart of the configuration data area judgment function described in the embodiment of the present invention is described in detail as follows:

[0069] Configuring the data area judgment function, the configuration data area judgment function specifically includes:

[0070] Configure the judgment function of the repeated data area, sparse data area, and random data area:

[0071] The data area in which data is repeated in units of single byte, data in unit of double byte, and data in unit of four bytes, and which lasts for the first set range is determined as a repeated data area.

[0072] In units of four bytes, the high-order 3 bytes remain unchanged, and the data of the fourth byte changes, and the area with a large continuous range is judged as a sparse data area;

[0073] The area other than the above two without regularity, or the second set range of repeated data and sparse data continuous range, is determined as a random data area;

[00...

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Abstract

The invention is suitable for the technical field of the FPGA(Field Programmable Gate Array), and provides a FPGA binary file compression and decompression method, and a FPGA binary file compression and decompression device. The compression method comprises the following steps: obtaining a FPGA binary file; traversing the contents of the FPGA binary file, classifying the contents, and judging classification data and a data area where the classification data is positioned; adopting a coding storage way corresponding to the data area to code and store the classification data; and according to a general compression algorithm, carrying out integral compression on the classification data of which the information entropy is smaller than a set value. The compression method has the following beneficial effects: 1) the structural characteristics of the FPGA binary file are analyzed, the FPGA binary file is divided into multiple data areas of specific types, and different coding ways are adopted for different data areas to carry out compression storage so as to greatly reduce a file storage space; and 2) the ways of length, type and data value are adopted for storing files, and are especially effective for an application scene of multi-time decompression and one-time compression. Decompression speed is far higher than compression speed, and a decompression effect is improved.

Description

technical field [0001] The invention belongs to the field of FPGA technology, and in particular relates to an FPGA binary file compression and decompression method and a compression and decompression device. Background technique [0002] Data compression refers to reducing the amount of data to reduce storage space without losing useful information, improving its transmission, storage and processing efficiency, or reorganizing data according to a certain algorithm to reduce data redundancy and storage space a technical method. The existing compression algorithms are general-purpose compression, and LZMA, GZIP, RAR, etc. are all general-purpose compression algorithms. [0003] However, the current general-purpose compression algorithm cannot optimize compression according to the data type of the FPGA binary file, which is not conducive to improving the overall compression ratio and overall compression performance. The reason is that the current general-purpose compression a...

Claims

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Application Information

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IPC IPC(8): G06F17/30H03M7/30
CPCG06F16/1744H03M7/30
Inventor 郭汇江
Owner 深圳市恒扬数据股份有限公司
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