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test handler

A technology for testing processors and testing rooms, which is applied in semiconductor/solid-state device testing/measurement, electrical components, circuits, etc., and can solve problems such as increasing the time for transferring semiconductor packaging

Active Publication Date: 2019-06-14
SEMES CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] However, aligning buffer trays and sorting buffer trays increases the time required to transfer semiconductor packages

Method used

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Embodiment Construction

[0026] Hereinafter, specific embodiments will be described in detail with reference to the accompanying drawings. This invention, however, may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0027] In this specification, it should be understood that when an element (layer) is referred to as being arranged on or connected to another element (layer) and / or arranged or connected to another element (layer), the element (layer) may be ) is directly arranged on or connected to another element (layer) or arranged or connected to another element (layer), or an intervening element (layer) may also be present. On the other hand, it will be understood that when an element is referred to as being directly disposed on or connected to another element, interveni...

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PUM

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Abstract

A test processor includes a load stacker for receiving a first customer tray in which a semiconductor package is housed, a loading portion for transferring the first customer tray from the load stacker to the load zone and directly transferring the semiconductor package from the first customer tray to the test tray arranged in the load zone, an inspection camera arranged above the transfer path of the first customer tray and for checking whether the semiconductor package is normally accommodated in the first customer tray, a test chamber arranged at a position adjacent to the loading section and for testing the electrical characteristics of the semiconductor package accommodated in the test tray, an unloading portion disposed adjacent the test chamber and adapted to transfer the semiconductor package directly from the test tray to a second customer tray disposed in an unloading zone adjacent the test chamber, and an unloader stacker for receiving the second customer tray.

Description

technical field [0001] The present disclosure relates to a test handler, and more particularly, to a test handler that processes a semiconductor package to electrically connect the semiconductor package to a test device for testing electrical characteristics of the semiconductor package. Background technique [0002] By repeatedly performing a series of manufacturing processes, a semiconductor chip can be formed on a silicon wafer as a semiconductor substrate, and the semiconductor chip can be individualized by a dicing process. By packaging a semiconductor chip, a semiconductor package can be manufactured. [0003] A semiconductor package can be judged as a non-defective product or a defective product through an electrical testing process. During the electrical testing, a test handler for handling the semiconductor package and a tester for testing the semiconductor package may be used. [0004] The test handler may include: a loader for transferring the semiconductor pack...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66
CPCH01L22/10
Inventor 李在东金成峰金应秀徐明洙
Owner SEMES CO LTD