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Branch predictor and method for operating the branch predictor

A technology of predictors and branches, applied in the direction of instruments, memory systems, machine execution devices, etc.

Active Publication Date: 2019-07-05
VIA ALLIANCE SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This is challenging because the location of branch instructions within a block is relatively random

Method used

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  • Branch predictor and method for operating the branch predictor
  • Branch predictor and method for operating the branch predictor
  • Branch predictor and method for operating the branch predictor

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Experimental program
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Embodiment Construction

[0011] vocabulary

[0012] To hash two or more entities, such as addresses and branch patterns, means to perform one or more ANDs on one or more bits of each of the two or more entities / or logical operations to produce a result with fewer digits than the largest entity of two or more entities. One or more AND / OR logic operations may include, but are not limited to: selection of pre-positioned entities; Boolean logic operations including exclusive OR (XOR), NAND, AND, OR, NOT, cyclic shift translation; and addition , subtraction, multiplication, division, and modulo arithmetic operations. To illustrate by example, assume a 100-bit branch history, a 32-bit address, and the result is a 10-bit index. Hashing the address and branch history (i.e., hashing the address and branch history) may involve combining bits [9:0] and bits [19:10] of the branch history with bits [9:10] of the branch instruction address 0] XOR.

[0013] In the branch predictor in the embodiment, the directi...

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Abstract

A branch predictor and method for operating the branch predictor are provided. The branch predictor contains block addresses and first / second byte offsets within the block of instruction bytes that can be used to access the block of instruction bytes of the instruction cache. The hash logic performs a hash operation on the branch pattern and the first / second address formed by the block address and each first / second byte offset to generate each first / second index. The conditional branch predictor receives the first / second index and in response thereto provides a first / second directional prediction of the first / second conditional branch instruction in the block of instruction bytes, respectively. In one embodiment, a branch target address cache (BTAC) provides byte offsets, and first / second direction predictions are statically associated with first / second target addresses also provided by BTAC. Alternatively, the byte offset is a predetermined value and the first / second direction prediction is dynamically associated with the first / second target address based on the relative size of the byte offset provided by the BTAC.

Description

technical field [0001] The present invention relates to the field of processor design, in particular to a plurality of addresses formed by a block address and a plurality of byte offsets and a branch instruction history transfer formed by a hash operation of a plurality of conditional branch instruction predictor index branches predictor. Background technique [0002] It is well known in the field of processor design that higher and higher prediction accuracy requirements are placed on branch instruction predictors. This requirement is intensified as processor pipeline levels, cache memory access latencies, and instruction issue widths in superscalar architectures increase. The branch instruction predictor includes predicting the target address, and predicting the direction of the conditional branch instruction, that is, jump or not jump. [0003] Typically, instructions are fetched from the instruction cache in units of relatively large blocks, for example, 16-byte instru...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38
CPCG06F9/3848G06F9/3806G06F9/3005G06F9/30047G06F12/0875G06F2212/452
Inventor 王小玲杨梦晨陈国华
Owner VIA ALLIANCE SEMICON CO LTD