A processing method and structure of an ultra-thin coreless packaging substrate
A technology for packaging substrates and processing methods, which is applied in the manufacture of electrical components, electrical solid devices, semiconductors/solid devices, etc., can solve the problems of insufficient strength of ultra-thin coreless packaging substrates, easy deformation and warping, product breakage, etc., to achieve Easy to process, avoid deformation and warping, and easy to transport
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Embodiment 1
[0023] Please refer to figure 1 The embodiment of the present invention provides a processing method of an ultra-thin coreless packaging substrate, which is applied in the field of packaging substrates, including but not limited to the field of integrated circuit packaging such as memory modules and micro-electromechanical systems. The method of the embodiment of the present invention helps to improve the processing ability of coreless packaging substrate products, and can be used to solve the processing of coreless packaging substrate products with a thickness of more than 100 μm, and can be especially used for processing coreless packaging substrate products below 100 μm. To reduce product damage, improve product yield, and meet the demand for mass production.
[0024] Please refer to figure 1 , The method of the embodiment of the present invention may include:
[0025] 101. Provide a carrier board, the carrier board includes a central dielectric layer and a composite copper foil...
Embodiment 2
[0075] Please refer to Figure 2l The second embodiment of the present invention also provides an ultra-thin coreless packaging substrate structure, which can be processed by the method of the first embodiment of the present invention.
[0076] Such as Figure 2l , Ultra-thin coreless packaging substrate structure can include:
[0077] An ultra-thin coreless packaging substrate 30, and a support plate 40 bonded to the ultra-thin coreless packaging substrate;
[0078] The coreless package substrate 30 includes an insulating layer 302, and a first circuit layer 301 and a second circuit layer 305 disposed on both sides of the insulating layer. The second circuit layer 305 and the first circuit layer 301 are electrically connected. Hole 304 is electrically connected;
[0079] The first circuit layer 301 is an embedded circuit buried in the insulating layer 302;
[0080] The supporting plate 40 is located on the side where the second circuit layer 305 is located.
[0081] Optionally, the sup...
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Abstract
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