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Readout self-check circuit of programmable memory and method

A self-test circuit and memory technology, applied in static memory, read-only memory, information storage, etc., can solve the problems of lower reliability and stability, final read data error, data sampling and latch error, etc., so as to be easy to know , optimize readout performance, and improve accuracy

Active Publication Date: 2017-02-22
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, under different working conditions of the memory, under the influence of manufacturing process, ambient temperature, working voltage, noise and other factors, the transmission of data has various delays or advances, which is different from the theoretical design, resulting in the readout from the storage unit. Errors or data sampling latch errors, these errors lead to errors in the final read data, affect the read performance of the memory, and reduce reliability and stability

Method used

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  • Readout self-check circuit of programmable memory and method
  • Readout self-check circuit of programmable memory and method

Examples

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Effect test

Embodiment 1

[0039] Such as figure 1 As shown, this is a one-bit data readout self-test circuit, the input of which is one-bit line data, and is latched by the transmission gate controlled by the pre-charge control signal. When the chip area is limited, or only for a certain redundant row of bit lines, or only for a certain special default memory row, this can be applied to the data readout self-test for only a certain bit.

[0040] The data input by the read self-test circuit is closely related to the address of the programmable memory. When the address of the programmable memory successfully hits a certain storage unit, and the data stored in the storage unit is logic 0, the read self-test corresponding to the storage unit The input data at the input end is a logic 1, and the logic 1 is latched by the transmission gate controlled by the precharge control signal to ensure that the sampled data is correct. When the address of the programmable memory successfully hits a certain storage uni...

Embodiment 2

[0044] Such as figure 2 as shown, figure 2 compared to figure 1 Expand one input into eight-bit data input, expand the two-input NOR gate into a multi-input NOR gate, and the rest of the components are the same as figure 1 Exactly the same, in the case of unlimited chip area, this can be applied to the data self-testing of the programmable memory full chip.

[0045] Here, it is assumed that the data storage unit where Data1 is located is selected by the address, and Data2-8 is not selected by the address; correspondingly, no storage unit where Data2-8 is located stores logic 0 or logic 1, and Data2-8 are all logic 0. Here, assuming that the data storage unit where Data1 is located stores data logic 1, Data1 is logic 0. After Data1-8 pass through the first transmission path, only data1 is transmitted to the input terminal of the first inverter due to the control of address decoding. If there is no error in the data transmission path, the result is correspondingly logic 0, ...

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Abstract

The invention discloses a readout self-check circuit of a programmable memory and a method. The readout self-check circuit comprises a two-input exclusive-OR gate and a ternary inverter, wherein the two-input exclusive-OR gate is used for detecting a difference before and after one bit of data passes through a data transmission channel; the ternary inverter is used for controlling whether the data transmitted via the data transmission channel is outputted to a final port or not, and an enabling control end of the ternary inverter is controlled by the output of the two-input exclusive-OR gate; the input of the readout self-check circuit can be extended into multiple bits of data, and each input firstly passes through a multi-input NOR gate to serve as one input of the two-input exclusive-OR gate, so as to detect the difference before and after the multiple bits of data pass through the data transmission channel. The readout self-check circuit has the advantages that the data error produced on the data transmission channel can be detected, and the readout performance of the programmable memory is optimized.

Description

technical field [0001] The invention relates to the field of programmable memory, in particular to a memory data readout self-check circuit and method. Background technique [0002] The core mechanism of traditional programmable memory data reading is to perform PWM modulation on the narrow pulse generated by the address signal jump detection circuit based on the pulse stretching circuit. PWM modulation will generate two extremely important signals. One is the pre-charge control The second is the data sampling pulse signal. These two signals control the reading and latching of data from the memory storage unit, as well as the transmission and on-off of data in the data transmission path. First, the pre-charge control signal generated from the PWM modulation module controls the pre-charge control circuit; the main function of the pre-charge control circuit is to generate a charging current to each sense amplifier through the pre-charge transistor and the discharge transistor,...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/26G11C16/34
Inventor 李建军张钦山
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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