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A programmable memory readout self-test circuit and method

A self-test circuit and memory technology, applied in static memory, read-only memory, information storage, etc., can solve the problems of lower reliability and stability, final read data error, data sampling and latch error, etc., so as to be easy to know , optimize readout performance, and improve accuracy

Active Publication Date: 2019-09-10
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, under different working conditions of the memory, under the influence of manufacturing process, ambient temperature, working voltage, noise and other factors, the transmission of data has various delays or advances, which is different from the theoretical design, resulting in the readout from the storage unit. Errors or data sampling latch errors, these errors lead to errors in the final read data, affect the read performance of the memory, and reduce reliability and stability

Method used

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  • A programmable memory readout self-test circuit and method
  • A programmable memory readout self-test circuit and method

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Embodiment 1

[0039] like figure 1 As shown, this is a one-bit data readout self-test circuit, and its input is one-bit line data, which is latched by the transmission gate controlled by the pre-charge control signal. When the chip area is limited, or only for a certain redundant row of bit lines, or only for a certain special default memory row, this can be applied to the data readout self-test for only a certain bit.

[0040] The data input by the read self-test circuit is closely related to the address of the programmable memory. When the address of the programmable memory successfully hits a certain storage unit, and the data stored in the storage unit is logic 0, the read self-test corresponding to the storage unit The input data at the input end is a logic 1, and the logic 1 is latched by the transmission gate controlled by the precharge control signal to ensure that the sampled data is correct. When the address of the programmable memory successfully hits a certain storage unit, and...

Embodiment 2

[0044] like figure 2 as shown, figure 2 compared to figure 1 Expand one input into eight-bit data input, expand the two-input NOR gate into a multi-input NOR gate, and the rest of the components are the same as figure 1 Exactly the same, in the case of unlimited chip area, this can be applied to the data self-testing of the programmable memory full chip.

[0045] Here, it is assumed that the data storage unit where Data1 is located is selected by the address, and Data2-8 is not selected by the address; correspondingly, no storage unit where Data2-8 is located stores logic 0 or logic 1, and Data2-8 are all logic 0. Here, assuming that the data storage unit where Data1 is located stores data logic 1, Data1 is logic 0. After Data1-8 pass through the first transmission path, only data1 is transmitted to the input terminal of the first inverter due to the control of address decoding. If there is no error in the data transmission path, the result is correspondingly logic 0, and...

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Abstract

The invention discloses a readout self-inspection circuit and method of a programmable memory; the readout self-inspection circuit includes: a two-input XOR gate, which is used to detect the similarity and difference of one-bit data before and after passing through the data transmission path; : a three-state inverter, used to control whether the data transmitted through the data transmission path is output to the final port, and its enabling control terminal is controlled by the output of the above-mentioned two-input XOR gate; the readout self-test circuit, its The input can also be extended to multi-bit data, and each input is first passed through a multi-input NOR gate and then used as an input of the above-mentioned two-input XOR gate, so as to detect similarities and differences between multi-bit data before and after passing through the data transmission channel. The invention can detect data errors generated on the data transmission path, and optimize the readout performance of the programmable memory.

Description

technical field [0001] The invention relates to the field of programmable memory, in particular to a memory data readout self-check circuit and method. Background technique [0002] The core mechanism of traditional programmable memory data reading is to perform PWM modulation on the narrow pulse generated by the address signal jump detection circuit based on the pulse stretching circuit. PWM modulation will generate two extremely important signals. One is the pre-charge control The second is the data sampling pulse signal. These two signals control the reading and latching of data from the memory storage unit, as well as the transmission and on-off of data in the data transmission path. First, the pre-charge control signal generated from the PWM modulation module controls the pre-charge control circuit; the main function of the pre-charge control circuit is to generate a charging current to each sense amplifier through the pre-charge transistor and the discharge transistor,...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/26G11C16/34
Inventor 李建军张钦山
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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