Error correction in case wom code is applied

Abstract

A method for storing bits in a memory cell is proposed, wherein a first and a second Wit are written into the same memory cell at the same address in two write processes following each other, and in the first write The storage unit is not erased after the process, wherein the first check bit is stored in the first further storage unit and the second check bit is stored in the second further storage unit. In addition, a corresponding device is described.

Description

technical field [0001] The scheme described here relates in particular to the storage of data in addressable memory. Background technique [0002] For example, data are written into the memory at one address in two successive write processes, and when data are written into the memory in a second write process following the first write process, no erase is required. The data written into the memory during the first write process and stored as state in the memory cells of the memory. [0003] In particular, a memory which has memory cells which can assume at least one first value and at least one second value as states is contemplated here, wherein the first value differs from the second value. The first value is represented here by way of example as 0 and the second value by way of example as 1. [0004] By way of example, the following assumes that the memory cell has the state 0 when the memory cell has the value 0 and that the memory cell has the state 1 when the memory ...

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Problems solved by technology

[0071] Furthermore, it is disadvantageous in the known WOM codes for identifying or correcting errors that, in the event of an address error, a further word is read from the memory instead of the desired word, but this further word cannot be recognized as erroneous because the additional word is a valid codeword stored at an additional (incorrectly determined here) address

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