UPI protocol model link layer module verification system based on UVM verification platform

Abstract

The invention discloses a UPI protocol model link layer module verification system based on a UVM verification platform, and the system comprises a UVM base class file which is used to perform UVM verification on a link layer module; and a parameter setting class file which integrates with the UVM base class file and is used to set a UVM environment internal variable parameter corresponding to the link layer module and a constraint parameter of the link layer module. By adding the parameter setting class file, the invention enables the link layer module in a UPI protocol model to be subjected to verification with application of the UVM verification platform and guarantees the verification efficiency of the link layer module.

Description

technical field [0001] The invention relates to the technical field of IC verification, in particular to a UPI protocol model link layer module verification system based on a UVM verification platform. Background technique [0002] With the increase of chip scale, verification in chip design has become the most expensive work in the process, accounting for an increasing proportion of the entire design cycle. The workload of verification has accounted for 70% to 80% of the entire SOC research and development, so improving the efficiency of chip verification has become crucial. UVM (Universal Verification Methodology, Universal Verification Methodology), originated from OVM, is a new generation of mature and open source verification methodology jointly launched by Cadence, Mentor and Synopsys. It uses the best verification framework to achieve coverage-driven Verification, which effectively combines the characteristics of test random generation, self-test platform and randomi...

AI Technical Summary

Problems solved by technology

At present, the link layer module cannot be verified by UVM platform, and the verification method adopted by it is less efficient than UVM.

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