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Physical unclonable function circuit utilizing monostable timing offset

A timing deviation, function circuit technology, applied in the direction of internal/peripheral computer component protection, etc., can solve the problems of complex anti-tamper protection circuits, vulnerable to intrusive attacks, etc.

Active Publication Date: 2017-03-29
NINGBO UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, traditional methods suffer from some challenges
First of all, since the key is stored in non-volatile memory in digital form, it is vulnerable to invasive attacks (Invasive Attacks, IA)
Secondly, for a higher level of information security, the chip needs to use complex anti-tamper protection circuits

Method used

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  • Physical unclonable function circuit utilizing monostable timing offset
  • Physical unclonable function circuit utilizing monostable timing offset
  • Physical unclonable function circuit utilizing monostable timing offset

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0022] Example 1: as figure 1 A physical unclonable function circuit using monostable timing deviation is shown, including 2(n+1) monostable timing circuits, n+1 two-input selection circuits and n arbitrators, where n is greater than or equal to 1 integer, the two-input selection circuit has a first input terminal, a second input terminal, a control terminal and an output terminal, the control terminal of the two-input selection circuit is used to access an external excitation signal, and the arbiter has a first input terminal, a second input terminal end and output end; the output end of the 2j+1 bit monostable timing circuit is connected with the first input end of the j+1 bit two-input selection circuit, and the output of the 2nd (j+1) bit monostable timing circuit terminal is connected with the second input terminal of the j+1th two-input selection circuit, wherein, j=0, 1, 2,..., n; the output terminal of the first two-input selection circuit is connected with the first a...

Embodiment 2

[0024] Embodiment 2: as figure 1 A physical unclonable function circuit using monostable timing deviation is shown, including 2(n+1) monostable timing circuits, n+1 two-input selection circuits and n arbitrators, where n is greater than or equal to 1 integer, the two-input selection circuit has a first input terminal, a second input terminal, a control terminal and an output terminal, the control terminal of the two-input selection circuit is used to access an external excitation signal, and the arbiter has a first input terminal, a second input terminal end and output end; the output end of the 2j+1 bit monostable timing circuit is connected with the first input end of the j+1 bit two-input selection circuit, and the output of the 2nd (j+1) bit monostable timing circuit terminal is connected with the second input terminal of the j+1th two-input selection circuit, wherein, j=0, 1, 2,..., n; the output terminal of the first two-input selection circuit is connected with the firs...

Embodiment 3

[0027] Example three: as figure 1 A physical unclonable function circuit using monostable timing deviation is shown, including 2(n+1) monostable timing circuits, n+1 two-input selection circuits and n arbitrators, where n is greater than or equal to 1 integer, the two-input selection circuit has a first input terminal, a second input terminal, a control terminal and an output terminal, the control terminal of the two-input selection circuit is used to access an external excitation signal, and the arbiter has a first input terminal, a second input terminal end and output end; the output end of the 2j+1 bit monostable timing circuit is connected with the first input end of the j+1 bit two-input selection circuit, and the output of the 2nd (j+1) bit monostable timing circuit terminal is connected with the second input terminal of the j+1th two-input selection circuit, wherein, j=0, 1, 2,..., n; the output terminal of the first two-input selection circuit is connected with the fir...

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Abstract

The invention discloses a physical unclonable function circuit utilizing monostable timing offset. The circuit comprises 2(n+1) monostable timing circuits, n+1 two-input selection circuits and n arbiters, wherein n is an integer larger than or equal to 1. An output end of a 2j+1 th monostable timing circuit is connected with a first input end of a j+1 two-input selection circuit. An output end of the 2j+1 th monostable timing circuit is connected with a second input end of the j+1 two-input selection circuit. j is equal to 0,1,2...,n. An output end of a first two-input selection circuit is connected with a first input end of a first arbiter. An output end of a k two-input selection circuit is connected with a second input end of a k-1 arbiter and a first input end of a k arbiter. K is equal to 2, 3...,n. An output end of a n+1 two-input selection circuit is connected with a second input end of a n arbiter. The physical unclonable function circuit utilizing monostable timing offset has following advantages: on the basis of higher reliability and uniqueness, high identifiability is obtained.

Description

technical field [0001] The invention relates to a physical non-clonable function circuit, in particular to a physical non-clonable function circuit utilizing monostable timing deviation. Background technique [0002] With the popularity of electronic devices, people rely more and more on information security chips to perform security-sensitive tasks. For example, electronic tags are often used for identity authentication, financial transactions to control smart cards, etc. The key to the security chip being able to perform these operations is how to implement device identity authentication and protect private information in a highly secure channel. At present, the usual method is to store the key in non-volatile memory or use cryptography to protect private information. However, traditional methods suffer from some challenges. First of all, since the key is stored in the non-volatile memory in digital form, it is vulnerable to intrusive attacks (Invasive Attacks, IA). Se...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F21/73
CPCG06F21/73
Inventor 钱浩宇汪鹏君蒋志迪丁代鲁
Owner NINGBO UNIV
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