Chip testing system and testing method

Abstract

The invention provides a chip test system and a test method. The internal part of the chip is provided with a controller, a Flash memory, an SRAM, and a BIST circuit. The test method includes: the controller reads configuration information suitable for the test of the SRAM from the Flash memory, wherein the configuration information is written from a test machine, and the test machine is coupled to a chip; the controller writes the configuration information to a special register corresponding to the BIST circuit; the controller writes test triggering information to the special register, and the BIST circuit automatically tests the SRAM when reading the test triggering information; and the controller receives a test result sent by the BIST circuit, performs operation processing on the test result, and sends an operation result corresponding to the operation processing to the test machine. By employing the scheme, the efficiency of the chip test can be improved.

Description

technical field [0001] The invention relates to the field of chip design, in particular to a chip testing system and testing method. Background technique [0002] Currently, when designing a chip, an embedded static random access memory (SRAM) is usually tested by using a built-in self test (BIST) circuit. The existing main test process of using BIST circuit to test SRAM is as follows: when testing, the BIST circuit automatically generates test vectors and test parameters such as SRAM control signals, address signals, data signals, and command signals, and sends them to the SRAM. Test the SRAM; receive the response data of the SRAM and compare it with the expected result, so as to realize the fault detection of the embedded SRAM. [0003] However, when the existing BIST method tests the embedded SRAM waiting for testing unit, the whole testing process depends on the implementation of the BIST circuit itself, which has the problem of low testing efficiency. Contents of the...

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Problems solved by technology

[0003] However, when the existing BIST method tests the embedded SRAM waiting test unit, the entire test process depends on the implementation of the BIST circuit itself, and there is a problem of low test efficiency

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