Power supply noise suppression device based on embedded capacitor substrate

Abstract

The invention discloses a power supply noise suppression device based on an embedded capacitor substrate, relating to the PDN design and test field. The power supply noise suppression device includes a VRM power supply network, an FPGA chip, a load module, a current and voltage sampling module, a three-way analog conditioning circuit and an SMA test interface that are arranged on the embedded capacitor substrate, the embedded capacitor substrate is a substrate based on an embedded capacitor, the current and voltage sampling module obtains the noisy sampling signal and the noise-free sampling signal by sampling the voltage signal, and the noisy sampling signal and the noise-free sampling signal are output to the corresponding sampling signal input end in the three-way analog conditioning circuit via the signal output end, and the three-way analog conditioning circuit amplifies the sampled signal at two stages and then outputs the amplified signal to the SMA test interface. The substrate based on the embedded capacitor can effectively suppress the PDN noise, thereby effectively saving the surface area of the circuit substrate, and the three-way analog conditioning circuit can be used for the measurement of the PDN noise.

Description

technical field [0001] The invention belongs to the field of power distribution network (Power Delivery Network, PDN) design and testing, and specifically uses embedded capacitors for effective suppression of PDN noise and uses three-way analog conditioning circuits for measurement of PDN current noise. Background technique [0002] After the digital IC enters the sub-micron / nanometer process, the clock frequency of the high-speed system reaches several GHz, the operating voltage drops below 1V, and the transient current soars to 50A / ns, which causes the PDN noise to seriously exceed the standard. Decoupling according to the PDN design criteria of domain target impedance will require dozens to hundreds of decoupling capacitors, occupying a large amount of circuit board surface area and increasing the complexity of PDN design. In addition, the power supply voltage of digital chips is getting lower and lower, and the allowable swing is getting smaller and smaller. In addition,...

AI Technical Summary

Problems solved by technology

[0002] After the digital IC enters the sub-micron / nanometer process, the clock frequency of the high-speed system reaches several GHz, the operating voltage drops below 1V, but the transient current soars to 50A / ns, which causes the PDN noise to seriously exceed the standard. Decoupling according to the PDN design criteria of domain target impedance will require dozens to hundreds of decoupling capacitors, occupying a large amount of circuit board surface area and increasing the complexity of PDN design

In addition, the power supply voltage of digital chips is getting lower and lower, and the allowable swing is getting smaller and smaller. In addition, it is more sensitive to noise. Based on traditional PDN measurement methods, direct measurement of voltage and current noise will introduce large measurement errors.

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