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A preprocessing method for splicing of subunit arrays

A sub-unit and preprocessing technology, applied in electrical digital data processing, special data processing applications, instruments, etc., can solve problems such as the decline of the efficiency of the layout level comparison tool, and achieve the speed of layout comparison, save memory, and reduce layout fragmentation. Effect

Active Publication Date: 2019-11-15
北京华大九天科技股份有限公司
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AI Technical Summary

Problems solved by technology

[0011] The present invention provides a subunit array splicing preprocessing method for an integrated circuit layout level comparison tool, which can solve the problem of a decrease in the efficiency of the layout level comparison tool caused by the level revision of the large array of cells in the layout

Method used

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  • A preprocessing method for splicing of subunit arrays
  • A preprocessing method for splicing of subunit arrays
  • A preprocessing method for splicing of subunit arrays

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Experimental program
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Embodiment Construction

[0025] as attached figure 1 Shown, the concrete realization process of the present invention is as follows:

[0026] Step (101), call all units according to hierarchical relationship, topologically sort, then go to step (102).

[0027] Step (102), according to the topological order, take out the next unprocessed unit, go to step (103).

[0028] Step (103), judging whether the current unit contains a subunit array or an instance, if so, go to step (104), otherwise the current unit does not operate, and directly goes to step (110).

[0029] Step (104), temporarily expand the array of subunits into Instance, save it in the temporary Instance container, and turn to step (105).

[0030] Step (105), sort the Instances in the temporary Instance container according to the placement point coordinates of the Instances, and go to step (106). The method of Instance topological sorting is as follows: according to the coordinates of the Instance placement points, they are first sorted ac...

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Abstract

The invention discloses a subunit array splicing pretreatment method of a very large scale integrated circuit layout hierarchy comparison tool, belongs to the semiconductor integrated circuit design automation field, and is mainly used for comparing the difference among integrated circuit layouts in rear end design. According to the pretreatment method, the problem that the layouts are disordered because of too many comparison tools when the subunit arrays among hierarchy layouts are inconsistent, thereby raising hierarchy layout comparison efficiency. The process comprises the steps of dispersing the array in each subunit in the layout as an instance (Instance), and ordering the instance with original instances of each subunit; when traversing ordered instances, constructing a Y-direction equal interval instance set and an X-direction equal interval instance set according to the position relation among the dispose points of the back and forth instances; after traversing, creating a new array and a residual instance after splicing according to the X-direction equal interval instance set and the Y-direction equal interval instance set to replace the original array and instance.

Description

technical field [0001] A very large-scale integrated circuit layout level comparison tool belongs to the field of semiconductor integrated circuit design automation back-end design, and relates to a layout subunit array splicing preprocessing method in the difference comparison operation of integrated circuit layout. Background technique [0002] Integrated circuit layout difference comparison is an operation frequently performed in the layout design and manufacturing process, and is usually used to screen the differences in graphics and text between two approximate layouts. [0003] During the design process, the layout is usually represented by a hierarchical structure, and the layout is composed of multiple cells (Cell). Units contain graphics, text data and instances of calling subunits (Instance). The main input data for the layout comparison tool is hierarchical layout data. [0004] There are two kinds of layout comparison tools: hierarchical comparison tool and sca...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 戴斌华于士涛王国庆路艳芳
Owner 北京华大九天科技股份有限公司
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