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Shift register and display device provided therewith

一种移位寄存器、电位的技术,应用在静态存储器、数字存储器信息、仪器等方向,能够解决异常动作和消耗电力增大等问题

Active Publication Date: 2017-05-10
SHARP KK
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As a result, abnormal operation and power consumption increase

Method used

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  • Shift register and display device provided therewith
  • Shift register and display device provided therewith
  • Shift register and display device provided therewith

Examples

Experimental program
Comparison scheme
Effect test

no. 1 approach >

[0105]

[0106] figure 2 It is a block diagram showing the overall configuration of the active matrix liquid crystal display device according to the first embodiment of the present invention. Such as figure 2 As shown, the liquid crystal display device includes: a power supply 100; a DC / DC converter 110; a display control circuit 200; a source driver (video signal line driving circuit) 300; a gate driver (scanning signal line driving circuit) 400; a drive circuit 500 ; and a display section 600 . In addition, in this embodiment, the gate driver 400 and the display unit 600 are formed on the same substrate (the TFT substrate which is one of the two substrates constituting the liquid crystal panel).

[0107] In the display part 600, there are formed: a plurality of (j) source bus lines (video signal lines) SL1˜SLj; a plurality (i) of gate bus lines (scanning signal lines) GL1˜GLi; The intersections of the bus lines SL1 to SLj and the plurality of gate bus lines GL1 to GLi...

no. 2 approach >

[0143] A second embodiment of the present invention will be described. In addition, only the points of difference from the first embodiment described above will be described.

[0144]

[0145] The overall configuration is the same as that in the above-mentioned first embodiment (refer to figure 2 ) are the same, therefore, the description is omitted. Figure 13 It is a block diagram showing the structure of the shift register 410 in the gate driver 400 in this embodiment. In the first embodiment described above, the scan signal output from the preceding stage is supplied as the set signal S to the constituent circuits SR of each stage. On the other hand, in the present embodiment, the scan signal output from the second preceding stage is supplied as the set signal S to each stage configuration circuit SR. That is, if Figure 14 As shown, for any stage (here set as the nth stage), the scan signal GOUT(n-1) output from the previous stage SR(n-1) is provided as the first c...

no. 3 approach >

[0162]

[0163] A third embodiment of the present invention will be described. The overall configuration is the same as that in the above-mentioned first embodiment (refer to figure 2 ) Likewise, therefore, the description is omitted. The configuration of the shift register 410 in the gate driver 400 is such that a configuration circuit SR of each stage is provided with an initialization signal (a signal for initializing the internal state of the configuration circuit SR of each stage immediately after the vertical scanning period starts) PS It is different from the above-mentioned second embodiment in that an input terminal for receiving a clear signal (a signal for clearing the internal state of each stage configuration circuit SR at the end of the vertical scanning period) CLR. That is, if Figure 19 As shown, the stage configuration circuit SR in this embodiment is provided with: an input terminal for receiving the first clock CKA; an input terminal for receiving the ...

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PUM

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Abstract

This invention implements a shift register, for driving a scanning-signal line, that makes it possible to reduce the bezel width and power consumption of a display device while ensuring reliability over long-term operation. In each of a number of stages, an output-control-node stabilization section (420) of a circuit constituting that stage comprises the following: a thin-film transistor (M5) wherein a fourth clock (CKD) that changes from an OFF level to an ON level when a scanning signal outputted by the previous stage is to change from an OFF level to an ON level is supplied to the gate terminal, the drain terminal is connected to an output-control node (NA), and the scanning signal outputted by the previous stage is supplied to the source terminal; and a thin-film transistor (M6) wherein a third clock (CKC) that changes from an OFF level to an ON level when a scanning signal outputted by the next stage is to change from an OFF level to an ON level is supplied to the gate terminal, the drain terminal is connected to the aforementioned output-control node (NA), and the scanning signal outputted by the next stage is supplied to the source terminal.

Description

technical field [0001] The present invention relates to an active matrix display device, and more specifically, to a shift register in a scanning signal line driving circuit for driving scanning signal lines provided in a display portion of the active matrix display device. Background technique [0002] Conventionally, there is known an active matrix liquid crystal display device including a display section including a plurality of source bus lines (video signal lines) and a plurality of gate bus lines (scanning signal lines). In such a liquid crystal display device, conventionally, a gate driver (scanning signal line driver circuit) for driving a gate bus line is often mounted as an IC (Integrated Circuit: integrated circuit) chip on the periphery of a substrate constituting a liquid crystal panel. . However, in recent years, a gate driver is increasingly formed directly on a TFT substrate which is one of two glass substrates constituting a liquid crystal panel. Such a ga...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C19/28G09G3/20G09G3/36G11C19/00
CPCG09G3/3677G09G2310/0286G09G2310/08G11C19/287G09G2300/0809G11C19/28
Inventor 末木俊次岩瀬泰章渡部卓哉田川晶原健吾
Owner SHARP KK
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