Chip packaging structure and manufacturing method therefor
A chip packaging structure and chip technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device parts, semiconductor devices, etc., can solve the problem of inability to realize rapid and uniform heat dissipation of multiple heterogeneous chips and discrete devices, which is not conducive to improving the system Level chip packaging heat dissipation efficiency and other issues
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[0043] Embodiments of the present invention will be described below with reference to the accompanying drawings.
[0044] see figure 1, in one embodiment of the present invention, a system-in-chip package structure 10 is provided, including a substrate 104, a plurality of chips 101, 102 and a plurality of discrete devices 103 are packaged on the upper surface of the substrate 104, and the substrate 104 The lower surface is provided with a plurality of solder balls 105 . In this embodiment, the chip 101 is packaged on the upper surface of the substrate 104 in the form of flip chip (Flip Chip), and the chip 102 is packaged on the upper surface of the substrate 104 in the form of wire bonding. , the plurality of discrete devices 103 are packaged on the upper surface of the substrate 104 in a surface mount manner. It can be understood that when the system-in-chip package structure 10 is working, the plurality of chips 101 , 102 and the plurality of discrete devices 103 are heat ...
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