Chip internal temperature monitoring equipment based on multi-chip stacking process
A technology for internal temperature and monitoring equipment, used in semiconductor/solid-state device components, semiconductor/solid-state device testing/measurement, semiconductor devices, etc., can solve problems such as failure to meet, test condition loopholes, etc., to reduce false rejections and flexibly configure , the experimental results are true and reliable
Active Publication Date: 2019-06-07
TIANJIN JINHANG COMP TECH RES INST
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Problems solved by technology
This kind of experimental process ignores the heat generated by the chip itself, but in fact, the heat generated by the chip itself under various operations still has a certain impact on the temperature of the chip's environment, especially in the -55°C low temperature test. At this time, the heat generated by the chip itself causes the environment where the chip is located to not reach -55°C. There are loopholes in such test conditions.
Method used
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Embodiment 1
[0031] This example figure 1 As shown, the micro temperature sensor chip is added in the design of the MCM chip, and then the temperature value corresponding to the point of the MCM chip is obtained by comparing the voltage value at both ends of the micro temperature sensor with the voltage reference point.
[0032] Such as figure 2 As shown, the film-encapsulated NTC thermistor chip size is 0.3mm×0.8mm×0.3mm. Its technological process is carried out in accordance with lead wire welding, insulation treatment, die punching, film packaging, cutting, marking, and corner cutting.
[0033] Give an example to illustrate the principle of chip placement of film-encapsulated NTC thermistors, such as image 3 As shown, the original MCM chip design contains two high-power consumption bare chips DSP and FPGA, so it is necessary to monitor the temperature changes of these two bare chips in the working state. However, in order to avoid the mutual influence of the chip heat of the film-e...
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The invention belongs to the technical field of chip packaging, and specifically relates to equipment for monitoring the internal temperatures of chips based on a multi-chip stacking technology. Specifically, a thin film packaging type NTC thermosensitive resistor is stacked on high power consumption bare chips on a multi-chip packaging substrate, and the temperature performance of the chips is realized by monitoring the internal temperatures of an output monitoring chip of the thermosensitive resistor, so that the monitoring for the internal temperatures of the chips is realized. Compared with the prior art, the equipment has the technical advantages that firstly, monitoring for the temperatures of a plurality of points inside the MCM chips can be realized; secondly, the temperature monitoring points can be flexibly configured, and the monitoring for the temperature state inside the MCM is realized by designing the MCM chips; thirdly, the maximum temperature when the MCM chips work in ordinary environmental conditions can be measured; and fourthly, temperature compensation for high and low temperature test conditions of the chips can be realized, so that the experimental result is more true and credible.
Description
technical field [0001] The invention belongs to the technical field of chip packaging, and specifically relates to a chip internal temperature monitoring device based on a multi-chip stacking process, specifically refers to stacking a thin-film packaged NTC thermistor on a high-power consumption bare chip on a multi-chip packaging substrate, through Monitor the output of the thermistor to monitor the internal temperature of the chip, so as to understand the temperature performance of the chip and realize the internal temperature monitoring of the chip. Background technique [0002] Multi-chip packaging means that MCM uses a multi-layer wiring substrate, and then connects multiple IC chips to the substrate by wire bonding, tape automatic bonding technology or controlled collapse chip connection method, so that they become components with specific functions. Its main advantages are higher circuit connection density and packaging efficiency, and compared with SMT, MCM packaging...
Claims
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IPC IPC(8): H01L21/66H01L23/31
CPCH01L2224/48091H01L2224/48465H01L2924/00014
Inventor 张楠朱天成李鑫候俊马王旭仇旭东
Owner TIANJIN JINHANG COMP TECH RES INST