Array substrate and preparation method thereof, display device

Abstract

The invention provides an array substrate and a preparation method of the array substrate, and a display device, and relates to the technical field of display. The invention can reduce the influence of resistance-capacitance delay of a grid line. The array substrate comprises the grid line arranged on the substrate, wherein one end of the grid line is a scanning signal input end, and moves along the direction far from the input end of the scanning signal; area of the cross section of the grid line is gradually increased; or both ends of the grid line are scanning signal input ends, and moves along the middle position of the input end of the scanning signal and the grid line; the area of the cross section of the grid line is gradually increased, wherein the cross section of the grid line is the section face on the grid line perpendicular to the extension direction of the grid line.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to an array substrate, a preparation method thereof, and a display device. Background technique [0002] With the development of display technology, people have higher and higher requirements on the display effect of the display panel. [0003] Such as figure 1 As shown, the display panel 11 is generally driven by a data driver 12 and a scan driver 13 located around it to display. The scan signal of the gate line is input by the scan driver 13 connected to the gate line to control the opening of a row of thin film transistors connected to the gate line, so that the data driver 12 can pass the data line through the open thin film transistor to the electrode 14 of the display panel 11 The voltage signal required for displaying the picture is input to realize the display on the display panel 11 . [0004] Among them, the resistance value of the grid line R=PL / S, P is the re...

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Problems solved by technology

[0005] Based on the above, since the resistance on the gate line gradually increases along the direction away from the scanning signal input end, the gate line generates RC Delay (resistance-capacitance delay), such as figure 1 As shown, the waveform of the scanning signal input to the grid line is distorted, that is, when the scanning signal with a normal waveform input from the scanning signal input terminal is transmitted along the extending direction of the grid line, the scanning signal will gradually be affected by the RC Delay of the grid line. reduce ( figure 1 The three waveforms of A, B, and C are image 3 The scanning signals received at the positions A, B, and C in the center) lead to different opening degrees of the thin film transistors, thereby causing the charging rate of the electrode 14 to gradually decrease along the direction away from the scanning signal input end, resulting in uneven brightness of the display panel and reducing the display Effect

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