Power supply clamping position ESD (electronic static discharge) protecting circuit

Abstract

The invention provides a power supply clamping position ESD (electronic static discharge) protecting circuit, comprising a power supply pin, a grounding pin, an R-C (resistance-capacitance) circuit, a trigger circuit, a biasing circuit and a clamping position circuit. The R-C circuit is used for inducting an ESD voltage and comprises an impedance component which is connected between the power supply pin and a first node, and a capacitive reactance component which is connected between the first node and a second node, wherein, the second node is not directly connected with the grounding pin; the trigger circuit is connected among the power supply pin, the grounding pin and the R-C circuit and is used for generating an ESD triggering signal according to the electrical levels of the first node and the second code; the biasing circuit is connected between the power supply pin and the grounding pin and is used for providing a biasing voltage for the second node; and the clamping circuit isconnected among the power supply pin, the grounding pin and the trigger circuit and is used for providing a low reluctance channel between a power supply and the ground after the ESD triggering signal is received so as to discharge an electrostatic current. The electric leakage current of an electronic static discharge protecting circuit can be effectively restrained by the power supply clamping position ESD protecting circuit, and an inner circuit is effectively protected to avoid the damage by static electricity.

Description

technical field [0001] The invention relates to the technical field of ESD (Electronic Static Discharge, electrostatic discharge) protection of semiconductor integrated chips, in particular to a clamping circuit between a power supply and a ground (power-to-ground) realized by using a bias circuit and feedback technology. Background technique [0002] During the packaging, testing, transportation, and manufacturing processes of IC (integrated circuit, integrated circuit) chips, various degrees of electrostatic discharge events will occur. Electrostatic discharge refers to the instantaneous process in which a large amount of charge is poured into the integrated circuit from the outside to the inside when an integrated circuit is floating. When the integrated circuit is discharged, an equivalent high voltage of hundreds or even thousands of volts will be generated, which will break down the gate oxide layer of the input stage in the integrated circuit. As the dimensions of tr...

AI Technical Summary

Problems solved by technology

[0008] In short, when no ESD event occurs, it is necessary to find a way to suppress the leakage current of the ESD protection circuit, so as not to cause false triggering of the ESD clamping circuit and other consequences

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