An Array Layout Generation Method for Full Board Layout Resistor and Capacitance Extraction

Abstract

Due to the development of touch screen and pixel design technologies, the resolution is increasingly high, the size is increasingly large, and a more severe challenge is provided to the rate of extraction of the resistance capacitance from the full-panel layout. The extraction of the resistance capacitance from the full-panel layout by directly using the traditional numerical analysis method is too time-consuming. The extractive process can be accelerated by using a simple-structure multiplexing-array layout. However, difficulty is brought for array-based extraction methods due to unremarkable array features of an original layout. The invention provides a multiplexing-array layout generation method, and the original layout is decomposed into multiplexing-array-containing new layouts through multiplexing pattern element size selection, layout cutting, area grouping and new layout generation technologies by using repeated pattern features. Thus, an array structure of the full-panel layout is reconstructed, and the method is used for accelerating the extraction of the resistance capacitance from the full-panel layout.

Description

technical field [0001] The array layout generation method is a method for extracting the resistance and capacitance of the full board layout, and the invention belongs to the field of EDA design. Background technique [0002] The rapid development of flat panel display (FPD) process technology poses great challenges to design tools. The calculation of resistors and capacitors directly affects the overall performance of the FPD. Fast and accurate extraction of resistors and capacitors from large-scale layouts has become one of the key technologies in FPD design tools. With higher resolution and larger design size, especially the popularity of the In Cell process and the requirement for full board design, the accurate calculation of the resistors and capacitors of the full board layout is more time-consuming. The speed of the traditional method is difficult to meet the design requirements. [0003] In the full board design of touch screen and pixels, the hierarchical design...

AI Technical Summary

Problems solved by technology

With the higher resolution and larger design size, especially the popularity of the In Cell process and the requirements for full board design, the accurate calculation of the full board layout resistors and capacitors is more time-consuming

The speed of traditional methods is difficult to meet the design requirements

[0003] In the full board design of touch screen and pixels, the hierarchical design method is usually adopted to make the touch screen unit and pixel unit into an array, but due to the access of other signal lines and the personal preference of the designer, the final layout hierarchy complex, array features no longer visibly present

Moreover, the graphics in the FPD layout are complex, and the precise extraction of resistors and capacitors is based on numerical analysis, and the speed is relatively slow.

Therefore, it is very time-consuming and even impossible to directly extract the resistors and capacitors of the full board layout.

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