A three-valued 4-81 line address decoder realized by cnfet

A technology of address decoder and inverter, applied in the field of 4-81 line address decoder, which can solve the problems of interconnection crosstalk and gate delay

Active Publication Date: 2018-09-18
NINGBO UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] The traditional address decoder is designed with CMOS technology. As the feature size shrinks to the nanometer level, problems such as gate delay and interconnect crosstalk caused by interconnection parasitic effects become more and more serious. The working speed of the address decoder encountered great challenges

Method used

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  • A three-valued 4-81 line address decoder realized by cnfet
  • A three-valued 4-81 line address decoder realized by cnfet
  • A three-valued 4-81 line address decoder realized by cnfet

Examples

Experimental program
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Embodiment

[0025] Example: such as figure 1 , figure 2 with image 3As shown, a three-valued 4-81 line address decoder realized by CNFET includes ten three-valued 2-9 line address decoders, and the three-valued 2-9 line address decoder has an enabling terminal, a first An input terminal, a second input terminal, a first output terminal, a second output terminal, a third output terminal, a fourth output terminal, a fifth output terminal, a sixth output terminal, a seventh output terminal, an eighth output terminal and a Nine output terminals; ten three-value 2-9 line address decoders are respectively the first three-value 2-9 line address decoder A1, the second three-value 2-9 line address decoder A2, and the third three-value 2-9 line address decoder A3, the fourth three-value 2-9 line address decoder A4, the fifth three-value 2-9 line address decoder A5, the sixth three-value 2-9 line address decoder A6, the seventh three-value 2-9 line address decoder A7, the eighth three-value 2-9...

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Abstract

The invention discloses a three-valued 4-81 line address decoder realized by utilizing CNFET. The three-valued 4-81 line address decoder comprises ten three-valued 2-9 line address decoders; each three-valued 2-9 line address decoder comprises two three-valued 1-3 line address decoders of the same structure, nine three-input NAND gates of the same structure and nine phase inverters of the same structure; each three-valued 1-3 line address decoder comprises a first CNFET tube, a second CNFET tube, a third CNFET tube, a fourth CNFET tube, a fifth CNFET tube, a sixth CNFET tube, a seventh CNFET tube, an eighth CNFET tube, a ninth CNFET tube, a tenth CNFET tube and an eleventh CNFET tube. The invention has the advantages of low power consumption and shorter delay.

Description

technical field [0001] The invention relates to a 4-81 line address decoder, in particular to a three-valued 4-81 line address decoder realized by CNFET. Background technique [0002] Static Random Access Memory (SRAM) has a fast reading and writing speed, and is often used as an interface circuit between a processor and a memory, and as a cache of the processor. With the development of VLSI (Very Large Scale Integration, VLSI), the processor clock frequency increases, which puts forward higher requirements on the read and write speed of SRAM. Address decoder is an important part of SRAM, and its address decoder delay accounts for a large part of SRAM read and write delay, so the read and write speed and power consumption of SRAM have a great influence on the performance of address decoder. relation. The design of the high-performance address decoder plays a great role in improving the reading and writing speed of SRAM and reducing the power consumption. [0003] Traditio...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C8/10G11C11/415
CPCG11C8/10G11C11/415
Inventor 汪鹏君龚道辉陈伟伟康耀鹏
Owner NINGBO UNIV
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