A three-valued 4-81 line address decoder realized by cnfet

Abstract

The invention discloses a three-valued 4-81 line address decoder realized by utilizing CNFET. The three-valued 4-81 line address decoder comprises ten three-valued 2-9 line address decoders; each three-valued 2-9 line address decoder comprises two three-valued 1-3 line address decoders of the same structure, nine three-input NAND gates of the same structure and nine phase inverters of the same structure; each three-valued 1-3 line address decoder comprises a first CNFET tube, a second CNFET tube, a third CNFET tube, a fourth CNFET tube, a fifth CNFET tube, a sixth CNFET tube, a seventh CNFET tube, an eighth CNFET tube, a ninth CNFET tube, a tenth CNFET tube and an eleventh CNFET tube. The invention has the advantages of low power consumption and shorter delay.

Description

technical field [0001] The invention relates to a 4-81 line address decoder, in particular to a three-valued 4-81 line address decoder realized by CNFET. Background technique [0002] Static Random Access Memory (SRAM) has a fast reading and writing speed, and is often used as an interface circuit between a processor and a memory, and as a cache of the processor. With the development of VLSI (Very Large Scale Integration, VLSI), the processor clock frequency increases, which puts forward higher requirements on the read and write speed of SRAM. Address decoder is an important part of SRAM, and its address decoder delay accounts for a large part of SRAM read and write delay, so the read and write speed and power consumption of SRAM have a great influence on the performance of address decoder. relation. The design of the high-performance address decoder plays a great role in improving the reading and writing speed of SRAM and reducing the power consumption. [0003] Traditio...

AI Technical Summary

Problems solved by technology

[0003] The traditional address decoder is designed with CMOS technology. As the feature size shrinks to the nanometer level, problems such as gate delay and interconnect crosstalk caused by interconnection parasitic effects become more and more serious. The working speed of the address decoder encountered great challenges

Images