Memory and bit line driver circuit

Abstract

The invention provides a memory and a bit line driving circuit. The bit line driving circuit comprises a first NMOS transistor, a first PMOS transistor, a second NMOS transistor and a second PMOS transistor; the grid electrode and drain electrode of the first NMOS transistor are connected with a first power end; the grid electrode of the first PMOS transistor is connected with a first input end, the source electrode of the first PMOS transistor is connected with the source electrode of the first NMOS transistor, and the drain electrode of the first PMOS transistor is connected with a first node; the grid electrode of the second NMOS transistor is connected with the first input end, the source electrode of the second NMOS transistor is connected with a second power end, and the drain electrode of the second NMOS transistor is connected with the first node; and the grid electrode of the second PMOS transistor is connected with a third power end, the drain electrode of the second PMOS transistor is connected with a bit line, and the source electrode of the second PMOS transistor is connected with the first node. When a programming operation is carried out on the memory, the highest voltage of the unselected bit line is the sum of the voltage of the third power end and the threshold voltage of the second PMOS transistor, and the voltage of the unselected bit line is clamped, so that the unselected bit line is prevented from forming high potential due to capacity coupling so as to carry out wrong operation on a storage unit.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to a memory and a bit line driving circuit. Background technique [0002] In the information age, information storage is one of the most important technical contents in information technology, and memories such as Electrically Erasable Programmable Read-Only Memory (EEPROM) and Flash memory (Flash) are more and more widely used. [0003] Memory structure diagram reference figure 1 As shown in , the memory includes a memory array formed by memory cells 101, a plurality of bit lines BL connected to the memory cells, a plurality of word lines WL and a plurality of control gate lines CG, through the bit lines BL, word lines WL and control gate lines The polar line CG implements selection and information access to the storage unit 101 . In order to access information of the storage unit 101 , such as performing a read operation or a programming operation on the storage unit, the memory ...

AI Technical Summary

Problems solved by technology

[0006] The purpose of the present invention is to provide a bit line driver circuit to solve the problem of misoperation of unselected bit lines due to capacitive coupling when programming memory cells in the prior art

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