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Device and method for improving multi-channel effective data transmission based on on-chip ram
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Al technical title is built by PatSnap Al team. It summarizes the technical point description of the patent document.
An effective data and multi-channel technology, applied in the direction of electrical digital data processing, architecture with a single central processing unit, digital computer components, etc., can solve the problems of not being able to reach 100%, slow reading speed, etc.
Active Publication Date: 2019-10-29
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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[0002] The sampling rate of digital systems is getting higher and higher, and the realization of high-speed data acquisition systems undoubtedly puts forward new requirements for the storage and processing capabilities of the massive data collected by the system; there are hundreds of megabytes of data flow into the memory per second, However, when the memory has a large output digital bandwidth, if the sampling data is to be transmitted to the host for processing through fast communication methods such as the PCI bus and USB interface, a huge bus bandwidth is required to transmit data in real time. It is difficult to achieve, so it is necessary to cache the high-speed data and upload it to the host to reduce the bus transmission pressure and host processing pressure
[0003] After research, it is found that domestic multi-channel data cache devices based on on-chip RAM mostly use a compatible design method to write multi-channel data into FIFO according to a compatible control method, but in this method, a maximum of N( N=2 x , x>0) channel data, but the user needs to cache q(2 x-1
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[0025] figure 1 It is a schematic diagram of the invention based on on-chip RAM to improve multi-channel effective data transmission.
[0026] In this example, if figure 1 As shown, the present invention is based on on-chip RAM to improve the device of multi-channel effective data transmission including 16-way multiplexer, ADC module, large-capacity memory and snapshot module, and a FIFO array, wherein, the multiplexer and FIFO array All implemented in the same FPGA, each ADC module ADC i . The snapshot module S corresponds to one input signal channel, i=1, 2, . . . , 16.
[0027] The method for improving the effective data transmission efficiency of 16 channels will be described in detail below in conjunction with the device, including the following steps:
[0028] S1, the signal conditioning channel CH i The input signal in is input to the corresponding ADC i Module, i=1,2,…,16, ADC i The module converts the received input signal into a digital signal DATA i , and sen...
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[0041] In order to better illustrate the technical effects of the present invention, a specific example is used for experimental verification. The user selects the data of the i(1,2,3...16) channel and sends it back to the host.
[0042] In the 16-channel data transmission device based on on-chip RAM, the ADC resolution is 16bit, the bit width of the input data stream is 256bit, the FIFO array has 5 FIFOs in total, and 2 FIFOs numbered A and B with a storage depth of 16bit×2k, input They are A_IN, B_IN, and the bit width is 16bit; 1 FIFO numbered C with a memory depth of 32bit×2k, the input is C_IN, and the bit width is 32bit; 1 FIFO numbered D is 64bit×2k, and the input is respectively It is D_IN, the bit width is 64bit; 1 FIFO numbered E with a storage depth of 128bit×2k, the input is E_IN, and the bit width is 128bit; the output bit width of all FIFOs is 32bit.
[0043] When the user selects i=1, the user chooses to transmit the data of one channel back to the host, and th...
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Abstract
The invention discloses a device and method for improving multi-channel effective data transmission based on an on-chip RAM. An ADC module performs analog-to-digital conversion on an input signal of a corresponding signal conditioning channel and stores it in a large-capacity memory. When a user needs data, the data It is read out of the large-capacity memory, and then the digital signal is tapped by the tapping module to reduce the frequency of the data stream of all channels. The multiplexer will select the data stream corresponding to the channel according to the number of channels of the buffer data selected by the user. It is sent to corresponding FIFOs with different numbers and different input bit widths for buffering.
Description
technical field [0001] The invention belongs to the technical field of data acquisition and storage systems, and more specifically relates to a device and method for improving multi-channel effective data transmission based on on-chip RAM. Background technique [0002] The sampling rate of digital systems is getting higher and higher, and the realization of high-speed data acquisition systems undoubtedly puts forward new requirements for the storage and processing capabilities of the massive data collected by the system; there are hundreds of megabytes of data flow into the memory per second, However, when the memory has a large output digital bandwidth, if the sampling data is to be transmitted to the host for processing through fast communication methods such as the PCI bus and USB interface, a huge bus bandwidth is required to transmit data in real time. It is difficult to achieve, so the high-speed data needs to be cached at the first level and then uploaded to the host ...
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