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Semiconductor package

A semiconductor and conductive layer technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc.

Inactive Publication Date: 2017-09-29
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Noisy electrical signals can cause serious problems in semiconductor packages

Method used

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  • Semiconductor package
  • Semiconductor package
  • Semiconductor package

Examples

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Embodiment Construction

[0110] The following disclosure provides many different embodiments, or examples, for implementing different features of the presented subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, the description below that a first feature is formed "on" a second feature or "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which the first feature is formed in direct contact. Embodiments where an additional feature may be formed between a feature and a second feature such that the first feature may not be in direct contact with the second feature. Additionally, this disclosure may reuse reference numbers and / or letters in various instances. Such re-use is for brevity and clarity and does not itself indicate a relationship between the v...

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Abstract

A semiconductor package comprises a first semiconductor element, an insulating layer and a second semiconductor element. The first conductor element comprises at least one conductive layer and at least one through hole layer. The insulating layer is arranged above the first semiconductor element and comprises at least one through insulator via (TIV) which extends from the first side of the insulating layer to the second side of the insulating layer. At least one through insulator via has a conductive core which comprises a copper-containing material. The second semiconductor element is arranged above the insulating layer and comprises at least one conductive layer and at least one through via layer. At least one through insulator via couples at least one via hole of the first semiconductor element to at least one via hole of the second semiconductor element.

Description

technical field [0001] Embodiments of the present invention relate to a semiconductor package and a manufacturing method thereof, and in particular to a semiconductor package having a through insulator via (TIV) with a specific structure and a manufacturing method thereof. Background technique [0002] Integrated circuits ("integrated circuits" (ICs)) are incorporated into many electronic devices. Integrated circuit packaging can vertically stack multiple integrated circuits in a "three-dimensional (3D)" package to save horizontal area on a printed circuit board ("printed circuit board, PCB"). An alternative packaging technique, referred to as 2.5D packaging, may use an interposer to couple one or more semiconductor die to a printed circuit board. The interposer may be formed of a semiconductor material such as silicon. Multiple integrated circuits or other semiconductor die (which may be of a heterogeneous technology) may be mounted on the interposer. [0003] Many devic...

Claims

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Application Information

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IPC IPC(8): H01L23/528
CPCH01L23/528H01L21/568H01L2224/04105H01L2224/12105H01L2224/16227H01L2224/19H01L2224/24137H01L2224/32225H01L2224/32245H01L2224/73267H01L2224/92244H01L2924/15192H01L2924/15311
Inventor 廖文翔郭丰维
Owner TAIWAN SEMICON MFG CO LTD
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