Parallel flash access system and method
A write access and bus technology, applied in the field of data communication, can solve problems such as inconsistent parallel FLASH access, lower access speed, and increased management complexity
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Embodiment 1
[0026] The embodiment of the present application discloses a parallel FLASH access system. refer to figure 1 As shown in , the system includes: a processor unit 11 , a programmable logic unit 12 and a parallel FLASH storage unit 13 . The processor unit 11 is connected to the programmable logic unit 12 through a local bus 14 , and the programmable logic unit 12 is connected to the parallel FLASH storage unit 13 through a controlled access bus 15 . refer to figure 2 As shown in , the controlled access bus 15 includes a byte configuration (BYTE_CFG) bus 153 .
[0027] The processor unit 11 described in this application may be a processor, and the processor described here may be a central processing unit (Central Processing Unit, CPU), or a specific integrated circuit (Application Specific Integrated Circuit, ASIC), or be One or more integrated circuits configured to implement embodiments of the present application. The programmable logic unit 12 may be a programmable process...
Embodiment 2
[0046] The embodiment of the present application discloses a parallel FLASH access method, which is applied to the above-mentioned system, referring to Figure 4 As shown in , the method includes:
[0047] S101. In an address cycle of bus access, the processor unit sends a read / write access address to the programmable logic unit through the local bus.
[0048] S102. The parallel FLASH storage unit is divided into two or more storage spaces, and the BOOT program space is stored and accessed according to the first bit width; the operating system and application program space are stored and accessed according to the second bit width; when read / write access When the address is located in the storage space of the startup BOOT program, the programmable logic unit configures the bus mode of the parallel FLASH storage unit to the first bit width through the byte configuration bus according to the read / write access address, and configures the BOOT program space with the first bit width...
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